Patents by Inventor Yi-Heng Li

Yi-Heng Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12237229
    Abstract: The present disclosure describes a method that includes forming a fin protruding from a substrate, the fin including a first sidewall and a second sidewall formed opposite to the first sidewall. The method also includes depositing a shallow-trench isolation (STI) material on the substrate. Depositing the STI material includes depositing a first portion of the STI material in contact with the first sidewall and depositing a second portion of the STI material in contact with the second sidewall. The method also includes performing a first etching process on the STI material to etch the first portion of the STI material at a first etching rate and the second portion of the STI material at a second etching rate greater than the first etching rate. The method also includes performing a second etching process on the STI material to etch the first portion of the STI material at a third etching rate and the second portion of the STI material at a fourth etching rate less than the third etching rate.
    Type: Grant
    Filed: May 25, 2023
    Date of Patent: February 25, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: I-Sheng Chen, Yi-Jing Li, Chen-Heng Li
  • Patent number: 12218197
    Abstract: A device includes a semiconductor nanostructure, and an oxide layer, which includes horizontal portions on a top surface and a bottom surface of the semiconductor nanostructure, vertical portions on sidewalls of the semiconductor nanostructure, and corner portions on corners of the semiconductor nanostructure. The horizontal portions have a first thickness. The vertical portions have a second thickness. The corner portions have a third thickness. Both of the second thickness and the third thickness are greater than the first thickness. A high-k dielectric layer surrounds the oxide layer. A gate electrode surrounds the high-k dielectric layer.
    Type: Grant
    Filed: August 3, 2023
    Date of Patent: February 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shu-Han Chen, Yi-Shao Li, Chun-Heng Chen, Chi On Chui
  • Patent number: 10036823
    Abstract: A method for monitoring and early warning of structural collapse, having following steps of: installing at least one electric field sensor in a monitoring area, wherein the at least one electric field sensor is used for measuring an electric field signal of the monitoring area; receiving the electric field signal and applying a signal analysis to the electric field signal; and issuing a warning signal when a critical transition feature occurs in the electric field signal to which the signal analysis is applied.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: July 31, 2018
    Assignee: National Central University
    Inventors: Chien-Chih Chen, Yi-Heng Li
  • Publication number: 20170146678
    Abstract: A method for monitoring and early warning of structural collapse, comprising following steps of: installing at least one electric field sensor in a monitoring area, wherein the at least one electric field sensor is used for measuring an electric field signal of the monitoring area; receiving the electric field signal and applying a signal analysis to the electric field signal; and issuing a warning signal when a critical transition feature occurs in the electric field signal to which the signal analysis is applied.
    Type: Application
    Filed: June 6, 2016
    Publication date: May 25, 2017
    Inventors: Chien-Chih Chen, Yi-Heng Li