Patents by Inventor Yi-Heng Liu
Yi-Heng Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240124163Abstract: A magnetic multi-pole propulsion array system is applied to at least one external cathode and includes a plurality of magnetic multi-pole thrusters connected adjacent to each other. Each magnetic multi-pole thruster includes a propellant provider, a discharge chamber, an anode and a plurality of magnetic components. The propellant provider outputs propellant. The discharge chamber is connected with the propellant provider to accommodate the propellant. The anode is disposed inside the discharge chamber to generate an electric field. The plurality of magnetic components is respectively disposed on several sides of the discharge chamber. One of the several sides of the discharge chamber of the magnetic multi-pole thruster is applied for one side of a discharge chamber of another magnetic multi-pole thruster.Type: ApplicationFiled: December 19, 2022Publication date: April 18, 2024Applicant: National Cheng Kung UniversityInventors: Yueh-Heng Li, Yu-Ting Wu, Chao-Wei Huang, Wei-Cheng Lo, Hsun-Chen Hsieh, Ping-Han Huang, Yi-Long Huang, Sheng-Wen Liu, Wei-Cheng Lien
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Patent number: 10796730Abstract: A semiconductor memory device includes a memory bank of an open bit-line architecture and a word-line decoder. The memory bank is divided into a plurality of memory blocks in a bit-line direction, and each of the memory blocks includes a plurality of word lines, a plurality of bit lines and a plurality of memory cells which are grouped into a plurality of memory sections including two edge memory sections and at least one non-edge memory section. The word-line decoder generates a plurality of word-line enabling signals based on a plurality of address signals and activates one of the word lines for each of the two edge memory sections of one of the memory blocks and one of the word lines for one of the at least one non-edge memory section of each of the other memory blocks concurrently in an active mode according to the word-line enabling signals.Type: GrantFiled: March 14, 2019Date of Patent: October 6, 2020Assignee: Elite Semiconductor Memory Technology Inc.Inventors: Yi Heng Liu, Jian-Sing Liou
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Publication number: 20200294570Abstract: A semiconductor memory device includes a memory bank of an open bit-line architecture and a word-line decoder. The memory bank is divided into a plurality of memory blocks in a bit-line direction, and each of the memory blocks includes a plurality of word lines, a plurality of bit lines and a plurality of memory cells which are grouped into a plurality of memory sections including two edge memory sections and at least one non-edge memory section. The word-line decoder generates a plurality of word-line enabling signals based on a plurality of address signals and activates one of the word lines for each of the two edge memory sections of one of the memory blocks and one of the word lines for one of the at least one non-edge memory section of each of the other memory blocks concurrently in an active mode according to the word-line enabling signals.Type: ApplicationFiled: March 14, 2019Publication date: September 17, 2020Inventors: Yi Heng LIU, Jian-Sing LIOU
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Patent number: 8368367Abstract: The invention provides a voltage regulator including a voltage divider and a power supply. The voltage divider circuit includes a first, second, third PMOS transistors, a first NMOS transistor, a pull down circuit, and a switching capacitor circuit. The pull down circuit includes a plurality of switches controlled by a pull down control signal. The switching capacitor circuit controlled by a first control pulse includes a capacitor and provides the capacitor connected to the dividing voltage for a short period while the power supply starts up to provide the input voltage. The power supply includes a comparator and a power voltage switch. The comparator compares the dividing voltage and a reference voltage and outputs a comparison result correspondingly. The power voltage switch is controlled by the comparison result to provide the input voltage from a power voltage.Type: GrantFiled: December 14, 2010Date of Patent: February 5, 2013Assignee: Elite Semiconductor Memory Technology Inc.Inventor: Yi-Heng Liu
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Patent number: 8330500Abstract: A comparator comprises a current mirror, a differential input pair, and a auxiliary circuit. The current mirror has a biasing end coupled to a power voltage, a first end, and a current outputting end coupled to an output node of the comparator. The differential input pair has a first and second input ends for respectively receiving a first voltage and a second voltage, a second and third ends, and a ground end, wherein the third end is coupled to the first end. The auxiliary circuit is coupled between the output node and the second end, and provides a minimum voltage of a comparison result output at the output node. The comparison result is the power voltage when the first voltage is larger than the second voltage, and the comparison result is the minimum voltage when the first voltage is less than the second voltage.Type: GrantFiled: November 25, 2010Date of Patent: December 11, 2012Assignee: Elite Semiconductor Memory Technology Inc.Inventor: Yi-Heng Liu
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Publication number: 20120146601Abstract: The invention provides a voltage regulator including a voltage divider and a power supply. The voltage divider circuit includes a first, second, third PMOS transistors, a first NMOS transistor, a pull down circuit, and a switching capacitor circuit. The pull down circuit includes a plurality of switches controlled by a pull down control signal. The switching capacitor circuit controlled by a first control pulse includes a capacitor and provides the capacitor connected to the dividing voltage for a short period while the power supply starts up to provide the input voltage. The power supply includes a comparator and a power voltage switch. The comparator compares the dividing voltage and a reference voltage and outputs a comparison result correspondingly. The power voltage switch is controlled by the comparison result to provide the input voltage from a power voltage.Type: ApplicationFiled: December 14, 2010Publication date: June 14, 2012Applicant: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.Inventor: Yi-Heng Liu
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Publication number: 20120133396Abstract: A comparator comprises a current mirror, a differential input pair, and a auxiliary circuit. The current mirror has a biasing end coupled to a power voltage, a first end, and a current outputting end coupled to an output node of the comparator. The differential input pair has a first and second input ends for respectively receiving a first voltage and a second voltage, a second and third ends, and a ground end, wherein the third end is coupled to the first end. The auxiliary circuit is coupled between the output node and the second end, and provides a minimum voltage of a comparison result output at the output node. The comparison result is the power voltage when the first voltage is larger than the second voltage, and the comparison result is the minimum voltage when the first voltage is less than the second voltage.Type: ApplicationFiled: November 25, 2010Publication date: May 31, 2012Applicant: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.Inventor: Yi-Heng Liu
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Patent number: 8076980Abstract: A temperature-compensated ring oscillator includes a control signal generator and a voltage controlled oscillator. The control signal generator is configured to generate at least one control signal, and includes at least one first resistor and second resistor. A first temperature coefficient of the first resistor is negative, and a second temperature coefficient of the second resistor is positive. The voltage controlled oscillator receives the control signal, outputs an oscillation signal, and has (2k+1) cascaded inverter units, where k?1. Each of the inverter units includes a first transistor, a second transistor and an inverter. The first transistor has a drain coupled to a first supply voltage and a gate to receive the control signal. The second transistor has a source to receive a second supply voltage and a gate to receive the control signal. The inverter is coupled between the first and the second transistors.Type: GrantFiled: January 19, 2010Date of Patent: December 13, 2011Assignee: Elite Semiconductor Memory Technology Inc.Inventor: Yi-Heng Liu
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Publication number: 20110175684Abstract: A temperature-compensated ring oscillator includes a control signal generator and a voltage controlled oscillator. The control signal generator is configured to generate at least one control signal, and includes at least one first resistor and second resistor. A first temperature coefficient of the first resistor is negative, and a second temperature coefficient of the second resistor is positive. The voltage controlled oscillator receives the control signal, outputs an oscillation signal, and has (2k+1) cascaded inverter units, where k?1. Each of the inverter units includes a first transistor, a second transistor and an inverter. The first transistor has a drain coupled to a first supply voltage and a gate to receive the control signal. The second transistor has a source to receive a second supply voltage and a gate to receive the control signal. The inverter is coupled between the first and the second transistors.Type: ApplicationFiled: January 19, 2010Publication date: July 21, 2011Applicant: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.Inventor: Yi-Heng Liu
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Patent number: 7759986Abstract: An integrated circuit comprises a first input node and a second input node, an output node; a first output transistor of a first type and a second output transistor of a second type, and a first clamping transistor of the second type and a second clamping transistor of a second type. The first clamping transistor, the first output transistor, the second clamping transistor, and the second output transistor are coupled in series across a first power supply terminal and a second power supply terminal. The first input node is coupled to a gate of the first output transistor. The second input node is coupled to a gate of the second output transistor. The output node is coupled to a common node of the first output transistor and the second clamping transistor. A gate of the first clamping transistor is coupled to a first reference voltage. A gate of the second clamping transistor is coupled to a second reference voltage.Type: GrantFiled: May 22, 2009Date of Patent: July 20, 2010Assignee: Elite Semiconductor Memory Technology IncInventors: Dar-Woei Wang, Yi-Heng Liu
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Publication number: 20090231016Abstract: An integrated circuit comprises a first input node and a second input node, an output node; a first output transistor of a first type and a second output transistor of a second type, and a first clamping transistor of the second type and a second clamping transistor of a second type. The first clamping transistor, the first output transistor, the second clamping transistor, and the second output transistor are coupled in series across a first power supply terminal and a second power supply terminal. The first input node is coupled to a gate of the first output transistor. The second input node is coupled to a gate of the second output transistor. The output node is coupled to a common node of the first output transistor and the second clamping transistor. A gate of the first clamping transistor is coupled to a first reference voltage. A gate of the second clamping transistor is coupled to a second reference voltage.Type: ApplicationFiled: May 22, 2009Publication date: September 17, 2009Applicant: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.Inventors: Dar-Woei Wang, Yi-Heng Liu
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Publication number: 20060152255Abstract: An integrated circuit comprises a first input node and a second input node, an output node; a first output transistor of a first type and a second output transistor of a second type, and a first clamping transistor of the second type and a second clamping transistor of the second type. The first clamping transistor, the first output transistor, the second clamping transistor, and the second output transistor are coupled in series across a first power supply terminal and a second power supply terminal. The first input node is coupled to a gate of the first output transistor. The second input node is coupled to a gate of the second output transistor. The output node is coupled to a common node of the first output transistor and the second clamping transistor. A gate of the first clamping transistor is coupled to a first reference voltage. A gate of the second clamping transistor is coupled to a second reference voltage.Type: ApplicationFiled: January 13, 2005Publication date: July 13, 2006Inventors: Dar-Woei Wang, Yi-Heng Liu