Patents by Inventor Yi-Hong Chen

Yi-Hong Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10896500
    Abstract: An image information display method, an image information display system and a display. The method includes: capturing a background image of the display; obtaining an object according the background image; capturing a relative movement information between a first user and the object; capturing a visual information corresponding to the first user; determining whether a reading comfort degree corresponding to the object meets a predetermined condition according to the relative movement information and the visual information; displaying a dynamic information corresponding to the object by the display when the reading comfort degree meets the predetermined condition; and not displaying the dynamic information corresponding to the object by the display when the reading comfort degree does not meet the predetermined condition.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: January 19, 2021
    Assignees: Industrial Technology Research Institute, Intellectual Property Innovation Corporation
    Inventors: Shin-Hong Kuo, Kuan-Ting Chen, Yu-Hsin Lin, Yi-Shou Tsai, Yu-Hsiang Tsai, Yi-Hsiang Huang
  • Patent number: 10891917
    Abstract: A transparent display system including a display panel, a data acquisition module and a computation module is provided. The data acquisition is adapted to capture a field luminance of a field where the display panel is located and a display information luminance of display information of the display panel. The computation module determines whether a luminance contrast of the display information falls within a range from a lower boundary to an upper boundary, wherein the luminance contrast of the display information equals to the field luminance plus the display information luminance and then divided by the field luminance. If it is determined that the luminance contrast of the display information does not fall within the range from the lower boundary to the upper boundary, a luminance contrast optimization procedure is performed. An operation method of the transparent display system is also provided.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: January 12, 2021
    Assignees: Industrial Technology Research Institute, Intellectual Property Innovation Corporation
    Inventors: Shin-Hong Kuo, Cheng-Chung Lee, Kuan-Ting Chen, Yi-Shou Tsai, Yu-Hsin Lin
  • Publication number: 20200403077
    Abstract: A method for fabricating semiconductor device includes the steps of first forming a silicon layer on a substrate and then forming a metal silicon nitride layer on the silicon layer, in which the metal silicon nitride layer includes a bottom portion, a middle portion, and a top portion and a concentration of silicon in the top portion is greater than a concentration of silicon in the middle portion. Next, a conductive layer is formed on the metal silicon nitride layer and the conductive layer, the metal silicon nitride layer, and the silicon layer are patterned to form a gate structure.
    Type: Application
    Filed: September 4, 2020
    Publication date: December 24, 2020
    Inventors: Chun-Chieh Chiu, Pin-Hong Chen, Yi-Wei Chen, Tsun-Min Cheng, Chih-Chien Liu, Tzu-Chieh Chen, Chih-Chieh Tsai, Kai-Jiun Chang, Yi-An Huang, Chia-Chen Wu, Tzu-Hao Liu
  • Patent number: 10845008
    Abstract: An LED filament comprises at least one LED section, a conductive section, two conductive electrodes and a light conversion layer. The conductive section is used to electrically connect two adjacent LED sections. The two conductive electrodes are electrically connected to each of the LED sections. Each of the LED sections includes at least two LED chips electrically connected to each other. The light conversion layer covers the LED sections, the conductive sections and the conductive electrodes, and a part of the two electrodes is exposed respectively. Since the LED filament includes the LED section and the conductive section, when the LED filament is bent, the stress is easily concentrated on the conductive section. Therefore, the breakage probability of the conductive wires connected within the LED section is reduced during bending. The quality of the LED filament and its application is improved.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: November 24, 2020
    Assignee: ZHEJIANG SUPER LIGHTING ELECTRIC APPLIANCE CO., LTD.
    Inventors: Tao Jiang, Wei-Hong Xu, Yukihiro Saito, Hayato Unagiike, Ai-Ming Xiong, Jun-Feng Xu, Yi-Ching Chen
  • Publication number: 20200364844
    Abstract: A method includes capturing a raw image from a semiconductor wafer, using graphic data system (GDS) information corresponding to the wafer to assign a measurement box in the raw image, performing a distance measurement on a feature of the raw image in the measurement box, and performing a manufacturing activity based on the distance measurement.
    Type: Application
    Filed: August 3, 2020
    Publication date: November 19, 2020
    Inventors: Peng-Ren CHEN, Shiang-Bau WANG, Wen-Hao CHENG, Yung-Jung CHANG, Wei-Chung HU, Yi-An HUANG, Jyun-Hong CHEN
  • Publication number: 20200350317
    Abstract: The present invention provides a storage node contact structure of a memory device comprising a substrate having a dielectric layer comprising a recess, a first tungsten metal layer, and an adhesive layer on the first tungsten metal layer and a second tungsten metal layer on the adhesive layer, wherein the second tungsten metal layer is formed by a physical vapor deposition (PVD).
    Type: Application
    Filed: July 16, 2020
    Publication date: November 5, 2020
    Inventors: Pin-Hong Chen, Tsun-Min Cheng, Chih-Chieh Tsai, Tzu-Chieh Chen, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang, Yi-Wei Chen, Hsin-Fu Huang, Chi-Mao Hsu, Li-Wei Feng, Ying-Chiao Wang, Chung-Yen Feng
  • Patent number: 10818819
    Abstract: A micro light emitting device including a component layer, a first electrode and a second electrode is provided. The component layer includes a main body and a protruding structure disposed on the main body. The first electrode is electrically connected to the component layer. The second electrode is electrically connected to the component layer. The first electrode, the second electrode and the protruding structure are disposed on the same side of the main body. The protruding structure is located between the first electrode and the second electrode. A connection between the first electrode and the second electrode traverses the protruding structure. The main body has a surface. The protruding structure has a first height with respect to the surface. Any one of the first electrode and the second electrode has a second height with respect to the surface. The relation 0.8?H1/H2?1.2 is satisfied, wherein H1 is the first height and H2 is the second height.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: October 27, 2020
    Assignee: PixeLED Display CO., LTD.
    Inventors: Pai-Yang Tsai, Fei-Hong Chen, Yi-Chun Shih
  • Patent number: 10817723
    Abstract: An information-display method for use in a transparent display is provided.
    Type: Grant
    Filed: August 16, 2018
    Date of Patent: October 27, 2020
    Assignees: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, INTELLECTUAL PROPERTY INNOVATION CORPORATION
    Inventors: Shin-Hong Kuo, Yi-Shou Tsai, Kuan-Ting Chen, Yu-Hsiang Tsai, Yu-Tang Tsai
  • Patent number: 10804365
    Abstract: A method for fabricating semiconductor device includes the steps of first forming a silicon layer on a substrate and then forming a metal silicon nitride layer on the silicon layer, in which the metal silicon nitride layer includes a bottom portion, a middle portion, and a top portion and a concentration of silicon in the top portion is greater than a concentration of silicon in the middle portion. Next, a conductive layer is formed on the metal silicon nitride layer and the conductive layer, the metal silicon nitride layer, and the silicon layer are patterned to form a gate structure.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: October 13, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chun-Chieh Chiu, Pin-Hong Chen, Yi-Wei Chen, Tsun-Min Cheng, Chih-Chien Liu, Tzu-Chieh Chen, Chih-Chieh Tsai, Kai-Jiun Chang, Yi-An Huang, Chia-Chen Wu, Tzu-Hao Liu
  • Patent number: 10802274
    Abstract: A transparent display system including a transparent display and a computation module is provided. The computation module is coupled to the transparent display. The computation module determines whether a display image displayed on the transparent display can be recognized based on display information and background information. If it is determined that the recognizability of the display image is poor, the haze of the background image displayed on the transparent display is adjusted. An operation method of the transparent display system is also provided.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: October 13, 2020
    Assignees: Industrial Technology Research Institute, Intellectual Property Innovation Corporation
    Inventors: Yu-Tang Tsai, Shin-Hong Kuo, Yi-Shou Tsai, Yi-Hsiang Huang, Wei-Lung Tsai, Kuan-Ting Chen
  • Patent number: 10794545
    Abstract: An LED light bulb having a bulb base and a bulb shell connected with the bulb base, the bulb shell having a layer of luminescent material formed in the material of the bulb shell. A stem with a stand extending to the center of the bulb shell is disposed in the bulb shell. A flexible LED filament is disposed in the bulb shell, at least half of the LED filament is disposed around a center axle of the LED light bulb, where the center axle is coaxial with the axle of the stand and two conductive supports, each of which are connected with the stem and the LED filament. A driving circuit is electrically connected with the two conductive supports and the bulb base. Additionally, a plurality of supporting arms has two ends, with one end connected to the stem and the other end connected to the LED filament.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: October 6, 2020
    Assignee: ZHEJIANG SUPER LIGHTING ELECTRIC APPLIANCE CO., LT
    Inventors: Tao Jiang, Wei-Hong Xu, Yukihiro Saito, Hayato Unagiike, Al-Ming Xiong, Jun-Feng Xu, Yi-Ching Chen
  • Patent number: 10777612
    Abstract: A pixel array including a plurality of pixel units is provided. Each of the pixel unit includes at least a first color subpixel, a second color subpixel and a Nth color subpixel, wherein N is an integer and N?3. The first color subpixel includes a first stacked light-emitting layer, the second color subpixel includes a second stacked light-emitting layer, and the Nth color subpixel includes a Nth stacked light-emitting layer. The first stacked light-emitting layer, the second stacked light-emitting layer, and the third stacked light-emitting layer each include a main light-emitting layer and an auxiliary light-emitting layer. The main light-emitting layer of the first color subpixel and the auxiliary light-emitting layer of the second color subpixel are the same material layer. The main light-emitting layer of the Nth color subpixel and the auxiliary light-emitting layer of the first color subpixel are the same material layer.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: September 15, 2020
    Assignee: Au Optronics Corporation
    Inventors: Hung-Chieh Hu, Yi-Hong Chen, Chung-Chia Chen, Meng-Ting Lee
  • Patent number: 10762621
    Abstract: A method includes capturing a raw image from a semiconductor wafer, assigning a measurement box in the raw image, arranging a pair of indicators in the measurement box according to graphic data system (GDS) information of the semiconductor wafer, measuring a distance between the indicators, and performing a manufacturing activity based on the measured distance.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: September 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Peng-Ren Chen, Shiang-Bau Wang, Wen-Hao Cheng, Yung-Jung Chang, Wei-Chung Hu, Yi-An Huang, Jyun-Hong Chen
  • Patent number: 10756090
    Abstract: The present invention provides a storage node contact structure of a memory device comprising a substrate having a dielectric layer comprising a recess, a first tungsten metal layer, and an adhesive layer on the first tungsten metal layer and a second tungsten metal layer on the adhesive layer, wherein the second tungsten metal layer is formed by a physical vapor deposition (PVD).
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: August 25, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Pin-Hong Chen, Tsun-Min Cheng, Chih-Chieh Tsai, Tzu-Chieh Chen, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang, Yi-Wei Chen, Hsin-Fu Huang, Chi-Mao Hsu, Li-Wei Feng, Ying-Chiao Wang, Chung-Yen Feng
  • Publication number: 20200266199
    Abstract: A method of manufacturing a semiconductor device for preventing row hammering issue in DRAM cell, including the steps of providing a substrate, forming a trench in the substrate, forming a gate dielectric conformally on the trench, forming an n-type work function metal layer conformally on the substrate and the gate dielectric, forming a titanium nitride layer conformally on the n-type work function metal layer, and filling a buried word line in the trench.
    Type: Application
    Filed: May 5, 2020
    Publication date: August 20, 2020
    Inventors: Chih-Chieh Tsai, Pin-Hong Chen, Tzu-Chieh Chen, Tsun-Min Cheng, Yi-Wei Chen, Hsin-Fu Huang, Chi-Mao Hsu, Shih-Fang Tzou
  • Publication number: 20200258889
    Abstract: A method of forming a bit line gate structure of a dynamic random access memory (DRAM) includes the following steps. A polysilicon layer is formed on a substrate. A sacrificial layer is formed on the polysilicon layer. An implantation process is performed on the sacrificial layer and the polysilicon layer. The sacrificial layer is removed. A metal stack is formed on the polysilicon layer. The present invention also provides another method of forming a bit line gate structure of a dynamic random access memory (DRAM) including the following steps. A polysilicon layer is formed on a substrate. A plasma doping process is performed on a surface of the polysilicon layer. A metal stack is formed on the surface of the polysilicon layer.
    Type: Application
    Filed: April 27, 2020
    Publication date: August 13, 2020
    Inventors: Yi-Wei Chen, Pin-Hong Chen, Tsun-Min Cheng, Chun-Chieh Chiu
  • Patent number: 10732738
    Abstract: A system module of customizing a screen image based on a non-invasive data-extraction system, and a method thereof are disclosed. The system module is applicable to a machine controller controlling a machine, and sensors are disposed around the machine. In the system module, an image capture device receives an image of an original screen from the machine controller, and transmits the image to the non-invasive data-extraction system for extracting information, and a software control system integrates data measured by the sensors with the information, and combined the integration result with a customized screen image, and an extra control component is embedded in an original operation screen of the machine controller. The customized screen image is shown on the machine controller to display information by more visual manner. Furthermore, the signal receiving device and an HID simulation device can be used to provide a basic function of a KVM switch.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: August 4, 2020
    Assignee: Adlink Technology Inc.
    Inventors: Chua-Hong Ng, Chao-Tung Yang, Wei-Hung Chen, Tsan-Ming Yu, Shih-Hsun Lin, Yang-Chung Tseng, Chih-Fu Hsu, Chien-Hsun Tu, Te-Cheng Chiu, Yi-Wei Lin, Jen-Chi Hsu
  • Publication number: 20200227264
    Abstract: A semiconductor device includes a gate structure on a substrate, in which the gate structure includes a silicon layer on the substrate, a titanium nitride (TiN) layer on the silicon layer, a titanium (Ti) layer between the TiN layer and the silicon layer, a metal silicide between the Ti layer and the silicon layer, a titanium silicon nitride (TiSiN) layer on the TiN layer, and a conductive layer on the TiSiN layer.
    Type: Application
    Filed: March 27, 2020
    Publication date: July 16, 2020
    Inventors: Tzu-Hao Liu, Yi-Wei Chen, Tsun-Min Cheng, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang, Po-Chih Wu, Pin-Hong Chen, Chun-Chieh Chiu, Tzu-Chieh Chen, Chih-Chien Liu, Chih-Chieh Tsai, Ji-Min Lin
  • Publication number: 20200215538
    Abstract: A self-driven microfluidic chip for rapid influenza A detection is provided. The chip includes: a substrate, a hydrophobic layer, a hydrophilic film layer, and a channel structure layer laminated sequentially. The structure of the channel structure layer includes a plurality of channels, a plurality of valves and reaction chambers in the channels, and a plurality of openings, wherein the hydrophilic film layer includes a pattern corresponding to the structure of the channel structure layer, and forms a disconnected area corresponding to the location of the valves to make the valves hydrophobic; the channel structure layer is formed of a flexible material, and heights of the valves are higher than those of the channels in a thickness direction of the channel structure layer in order to control liquid flow by pressing the valves.
    Type: Application
    Filed: April 25, 2019
    Publication date: July 9, 2020
    Inventors: GWO-BIN LEE, YU-DONG MA, HSI-PIN MA, PO-CHIUN HUANG, KUANG-HSIEN LI, YI-HONG CHEN, YUNG-MAO LEE
  • Patent number: 10685964
    Abstract: A semiconductor structure for preventing row hammering issue in DRAM cell is provided in the present invention. The structure includes a trench with a gate dielectric, an n-type work function metal layer, a TiN layer conformally formed within, and a buried word line filled in the trench.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: June 16, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chih-Chieh Tsai, Pin-Hong Chen, Tzu-Chieh Chen, Tsun-Min Cheng, Yi-Wei Chen, Hsin-Fu Huang, Chi-Mao Hsu, Shih-Fang Tzou