Abstract: This disclosure provides systems, methods, and devices for image processing that support enhanced white balancing operations. In a first aspect, a method of image processing includes receiving first image data obtained at a first aperture; determining a first output image frame based on the first image data by applying a first white balancing to at least a portion of the first image data; receiving second image data obtained at a second aperture; and determining a second output image frame based on the second image data by applying a second white balancing based on the first aperture and the second aperture to at least a portion of the second image data. The second white balancing may be based on a first compensation factor based on the first aperture and the second aperture used to adjust the first white balancing. Other aspects and features are also claimed and described.

Abstract: A method includes forming a dielectric layer over an epitaxial source/drain region. An opening is formed in the dielectric layer. The opening exposes a portion of the epitaxial source/drain region. A barrier layer is formed on a sidewall and a bottom of the opening. An oxidation process is performing on the sidewall and the bottom of the opening. The oxidation process transforms a portion of the barrier layer into an oxidized barrier layer and transforms a portion of the dielectric layer adjacent to the oxidized barrier layer into a liner layer. The oxidized barrier layer is removed. The opening is filled with a conductive material in a bottom-up manner. The conductive material is in physical contact with the liner layer.

Abstract: An ultrasonic mouse includes an ultrasonic module, a processing unit, and a transmission interface. The ultrasonic module includes an ultrasonic emitting element and a plurality of ultrasonic receiving elements, the ultrasonic receiving elements and the ultrasonic emitting element are arranged in a matrix, and the ultrasonic receiving elements are arranged surrounding the ultrasonic emitting element. The ultrasonic emitting element generates an ultrasonic signal. When the ultrasonic mouse moves, at least one of the ultrasonic receiving elements generates sensing information upon receiving the ultrasonic signal. The processing unit is electrically connected to the ultrasonic module, receives the sensing information, and calculates and generates a movement signal. The transmission interface is electrically connected to the processing unit, and transmits the movement signal out.

Abstract: Disclosed herein is the use a cyanobacterial biomass for treating hepatitis B virus (HBV) infection, in particular, chronic HBV infection. According to various embodiments of the present disclosure, the cyanobacterial biomass, upon administration of at least one month, significantly reduces the level of the surface antigen of hepatitis B virus (HBsAg) detectable in the subject receiving the treatment and/or mitigates insomnia associated with chronic HBV infection.

Abstract: A pixel circuit includes a driving transistor, a storage capacitor, a first transistor, a second transistor, a third transistor and a fourth transistor. A first end of the driving transistor is electrically coupled to a system high voltage terminal. The driving transistor is configured to control a driving current supplied to a light emitting element. A first end of the storage capacitor is electrically coupled to a control end of the driving transistor. A first end of the first transistor is electrically coupled to a second end of the storage capacitor, and a second end of the first transistor is configured to receive a data signal. When the first transistor is turned on according to the first control signal, the storage capacitor resets a voltage at the control end of the driving transistor, by a capacitive coupling effect, according to a change in voltage of the data signal.

Abstract: A lithium battery cell includes an upper cover module, a first battery electrode group, a second battery electrode group, and a plurality of first electrode connection straps. The first electrode connection straps are stacked together and have the same width and length. A first end of the first electrode connection straps is welded to a first tab, a second end of the first electrode connection straps is welded to a second tab, and a middle part of the first electrode connection straps is welded to a first electrode terminal. An even number of first bending parts are formed between the middle part and the first end, and an even number of second bending parts are formed between the middle part and the second end, and the first bending parts and the second bending parts are symmetrical to each other. Furthermore, a lithium battery cell manufacturing method is also disclosed therein.

Abstract: A proximity ultrasonic sensing apparatus includes a microprocessor and an ultrasonic sensing assembly. The microprocessor generates a control signal. The ultrasonic sensing assembly includes a boost circuit to boost the control signal into a driving signal, an ultrasonic transmitting module to generates and sends an ultrasonic signal according to the driving signal, an ultrasonic receiving module to converts reflection of the ultrasonic signal into a reflection signal, and an amplifying circuit to amplifies the reflection signal into a sensing signal. A transmitting/receiving angle of the ultrasonic transmitting module and the ultrasonic receiving module is in a range of 2 to 10 degrees. The microprocessor generates a sensing result according to the sensing signal. A frequency of the ultrasonic signal is in a range of 500 KHz to 1.2 MHz. A sensing distance of the ultrasonic sensing assembly is in a range of 0.2 to 8 centimeters.

Abstract: A spin orbit torque magnetoresistive random access memory (SOT MRAM) includes at least a spin current source alloy layer, a ferromagnetic free layer, and an insulation layer. The spin current source alloy layer is a nickel-tungsten alloy layer. The ferromagnetic free layer is located on the spin current source alloy layer. The insulation layer is located on the ferromagnetic free layer. Since the nickel-tungsten alloy layer has favorable perpendicular magnetic anisotropic and can maintain a high spin Hall angle, it is suitable as a spin current source for the SOT MRAM.

Abstract: The present disclosure provides a molding system for fabricating a FRP composite article. The molding system includes a detector, a resin dispenser, a processing module, and a molding machine. The detector is configured to capture a graph of a woven fiber from a top view. The resin dispenser is configured to provide a resin to the woven fiber to form a FRP. The processing module is configured to receive the graph and a plurality of parameters of the FRP. The processing module includes a CNN model, and is configured to use the CNN model to obtain a plurality of predicted mechanical properties of the FRP according to the graph and the plurality of parameters of the FRP. The molding machine is configured to mold the FRP to fabricate the FRP composite article according to the plurality of predicted mechanical properties.

Abstract: This disclosure is directed to a circuit that includes a substrate, a target device on the substrate, and an electrostatic discharge (ESD) device electrically coupled to the target device. The ESD device includes an ESD detection circuit electrically coupled to a first reference voltage supply and a second reference voltage supply, an inverter circuit electrically coupled to the ESD detection circuit and configured to trigger in response to an ESD event on the first or second reference voltage supply, a rectifier circuit electrically coupled to the inverter circuit and configured to rectify a current discharged from the inverter circuit, and a transistor electrically coupled to the rectifier circuit and configured to discharge a remaining current passing through the rectifier circuit.

Abstract: A display device includes a pixel circuit and a stage of a scan driver. The stage of the scan driver is electrically coupled to the pixel circuit. The stage of the scan driver is configured to output a first scan signal and a second scan signal to the pixel circuit. A first enable voltage of the first scan signal is at a first logic level, and a first disable voltage of the first scan signal is at a second logic level. A second enable voltage of the second scan signal is at the second logic level.

Abstract: A light-emitting device includes a semiconductor stack including a first semiconductor layer, a second semiconductor layer and an active area between the first semiconductor layer and the second semiconductor layer, wherein the first semiconductor layer including an upper surface; an exposed region formed in the semiconductor stack to expose the upper surface; a first protective layer covering the exposed region and a portion of the second semiconductor layer, wherein the first protective layer includes a first part with a first thickness formed on the upper surface and a second part with a second thickness formed on the second semiconductor layer, the first thickness is smaller than the second thickness; a first reflective structure formed on the second semiconductor layer and including one or multiple openings; and a second reflective structure formed on the first reflective structure and electrically connected to the second semiconductor layer through the one or multiple openings.

Abstract: A light-emitting device includes a substrate including a top surface, a first side surface and a second side surface, wherein the first side surface and the second side surface of the substrate are respectively connected to two opposite sides of the top surface of the substrate; a semiconductor stack formed on the top surface of the substrate, the semiconductor stack including a first semiconductor layer, a second semiconductor layer, and an active layer formed between the first semiconductor layer and the second semiconductor layer; a first electrode pad formed adjacent to a first edge of the light-emitting device; and a second electrode pad formed adjacent to a second edge of the light-emitting device, wherein in a top view of the light-emitting device, the first edge and the second edge are formed on different sides or opposite sides of the light-emitting device, the first semiconductor layer adjacent to the first edge includes a first sidewall directly connected to the first side surface of the substrate,

Abstract: The current disclosure describes techniques of protecting a metal interconnect structure from being damaged by subsequent chemical mechanical polishing processes used for forming other metal structures over the metal interconnect structure. The metal interconnect structure is receded to form a recess between the metal interconnect structure and the surrounding dielectric layer. A metal cap structure is formed within the recess. An upper portion of the dielectric layer is strained to include a tensile stress which expands the dielectric layer against the metal cap structure to reduce or eliminate a gap in the interface between the metal cap structure and the dielectric layer.

Abstract: An ultrasonic sensing element assembly includes a semiconductor substrate and a plurality of ultrasonic sensing elements on the semiconductor substrate and arranged in an array. Each of the ultrasonic sensing elements is in a sensing region of the semiconductor substrate. Each of the ultrasonic sensing elements includes a first sensing module with a first sensing unit and a second sensing unit connected in parallel, a second sensing module with a third sensing unit and a fourth sensing unit connected in parallel, four connection pads, and four welding pads. Each of the connection pads is in a through hole passing through a first surface and a second surface of the sensing region. The four welding pads are on the second surface of the sensing region and overlap vertical projections of the first sensing unit, the second sensing unit, the third sensing unit, and the fourth sensing unit respectively.

Abstract: A photographing optical lens system includes five lens elements being, in order from an object side to an image side along an optical path, a first lens element, a second lens element, a third lens element, a fourth lens element and a fifth lens element. Each lens element has an object-side surface facing the object side and an image-side surface facing the image side. The first lens element has positive refractive power and the object-side surface being convex in a paraxial region thereof. The image-side surface of the third lens element is convex in a paraxial region thereof. The object-side surface of the fourth lens element is convex in a paraxial region thereof. The fifth lens element has negative refractive power, the object-side surface being convex, and the image-side surface being concave in a paraxial region thereof.

Abstract: A lithium battery cell includes an upper cover module, a first battery electrode group, a second battery electrode group, and a plurality of first electrode connection straps. The first electrode connection straps are stacked together. A first end of the first electrode connection straps is welded to a first tab, a second end of the first electrode connection straps is welded to a second tab, and a middle part of the first electrode connection straps is welded to a first electrode terminal. An even number of first bending parts are formed between the middle part and the first end, and an even number of second bending parts are formed between the middle part and the second end, and the first bending parts and the second bending parts are symmetrical to each other. A lithium battery cell manufacturing method is also disclosed therein.

Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.

Abstract: A semiconductor structure includes a source/drain feature in the semiconductor layer. The semiconductor structure includes a dielectric layer over the source/drain feature. The semiconductor structure includes a silicide layer over the source/drain feature. The semiconductor structure includes a barrier layer over the silicide layer. The semiconductor structure includes a seed layer over the barrier layer. The semiconductor structure includes a metal layer between a sidewall of the seed layer and a sidewall of the dielectric layer, a sidewall of each of the silicide layer, the barrier layer, and the metal layer directly contacting the sidewall of the dielectric layer. The semiconductor structure includes a source/drain contact over the seed layer.

Abstract: An electronic component includes a first electronic unit including a plurality of pads, a first conductive layer, a second conductive layer, a first insulating layer having a first thickness, a second insulating layer having a second thickness, a second electronic unit, and a solder ball. The first conductive layer is disposed between the first electronic unit and the second conductive layer, and electrically connected to at least one of the pads through a conductive via. The first insulating layer is disposed between the first conductive layer and the second conductive layer. The second conductive layer is disposed between the first insulating layer and the second insulating layer. The first thickness is different from the second thickness. The second conductive layer is disposed between the first conductive layer and the second electronic unit. The second conductive layer is electrically connected to the second electronic unit through the solder ball.