Abstract: A switching board and a soldering method thereof are provided. The switching board includes a circuit board having a board body and a first metal ring, where the board body has a first surface, and the first metal ring is formed on the first surface and surrounds a periphery of the board body. The switching board further includes a first metal element disposed on the first surface and fastened to the first metal ring by soldering. The switching board has a high pressure resistance and a low leakage rate.

Abstract: A method of establishing a cancer screening model is provided, including: providing a plurality of samples and a plurality of corresponding cancer states; analyzing these samples by a low-resolution mass spectrometer to obtain a plurality of mass spectral data, wherein the low-resolution mass spectrometer is undertaken a mass accuracy level above 5 ppm and a mass resolution (m/?m) below 10,000; inputting these mass spectral data into a machine learning algorithm to obtain a plurality of markers by a feature selection method; and using these markers and these cancer states by the machine learning algorithms to establish cancer screening model.

Abstract: Semiconductor devices and methods of manufacture are provided wherein a metallization layer is located over a substrate, and a power grid line is located within the metallization layer. A signal pad is located within the metallization layer and the signal pad is surrounded by the power grid line. A signal external connection is electrically connected to the signal pad.

Abstract: A method includes forming a dielectric layer over an epitaxial source/drain region. An opening is formed in the dielectric layer. The opening exposes a portion of the epitaxial source/drain region. A barrier layer is formed on a sidewall and a bottom of the opening. An oxidation process is performing on the sidewall and the bottom of the opening. The oxidation process transforms a portion of the barrier layer into an oxidized barrier layer and transforms a portion of the dielectric layer adjacent to the oxidized barrier layer into a liner layer. The oxidized barrier layer is removed. The opening is filled with a conductive material in a bottom-up manner. The conductive material is in physical contact with the liner layer.

Abstract: A multiplexer circuit includes first and second fins each extending in an X-axis direction. First, second, third and fourth gates extend in a Y-axis direction perpendicular to the X-axis direction and contact the first and second fins. The first, second, third and fourth gates are configured to receive first, second, third and fourth data signals, respectively. Fifth, sixth, seventh and eighth gates extend in the Y-axis direction and contact the first and second fins, the fifth, sixth, seventh and eighth gates, and are configured to receive the first, second, third and fourth select signals, respectively. An input logic circuit is configured to provide an output at an intermediate node. A ninth gate extends in the Y-axis direction and contacts the first and second fins. An output logic circuit is configured to provide a selected one of the first, second, third and fourth data signals at an output terminal.

Abstract: A method according to the present disclosure includes receiving a workpiece that includes a first gate structure including a first cap layer thereon, a first source/drain contact adjacent the first gate structure, a second gate structure including a second cap layer thereon, a second source/drain contact, an etch stop layer (ESL) over the first source/drain contact and the second source/drain contact, and a first dielectric layer over the ESL. The method further includes forming a butted contact opening to expose the first cap layer and the first source/drain contact, forming a butted contact in the butted contact opening, after the forming of the butted contact, depositing a second dielectric layer, forming a source/drain contact via opening through the second dielectric layer, the ESL layer, and the first dielectric layer to expose the second source/drain contact, and forming a source/drain contact via in the source/drain contact via opening.

Abstract: An electronic component and a manufacturing method thereof are provided. The electronic component includes a structure member and a connecting member. The structure member includes at least one working unit. The at least one working unit is disposed in a first region. The connecting member is disposed on the structure member and includes a second region. The second region is overlapped with the first region, and a metal density of the second region is less than a metal density of the first region. The electronic component and the manufacturing method thereof of the embodiment of the disclosure include the effect of improving the reliability or quality of the electronic component.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a gate structure over a semiconductor substrate. The gate structure includes a gate electrode layer, a gate dielectric layer covering two opposite sidewalls and a bottom of the gate electrode layer, and two gate spacers correspondingly covering portions of gate dielectric layer that covers the two opposite sidewalls of the gate electrode layer. The method also includes forming a contact structure adjacent to one of the two gate spacers, successively recessing the contact structure and the one of the two gate spacers to form a recess that exposes the contact structure and the one of the two gate spacers, and forming a first insulating capping feature in the recess to cover and a top of the contact structure.

Abstract: A semiconductor device includes a substrate having a medium-voltage (MV) region and a logic region, a gate structure on the MV region, a first single diffusion break (SDB) structure and a second SDB structure in the substrate directly under the gate structure, and a source/drain region adjacent to two sides of the gate structure. Preferably, top surfaces of the first SDB structure and the second SDB structure are coplanar, bottom surfaces of the first SDB structure and the second SDB structure are coplanar, and the first SDB structure and the second SDB structure are made of same material.

Abstract: A phase shifter is provided, which includes a first substrate, a second substrate, a liquid crystal layer, a plurality of first ring-shaped electrodes and a plurality of second ring-shaped electrodes. The first substrate and the second substrate are disposed opposite to each other. The liquid crystal layer is disposed between the first substrate and the second substrate. The plurality of first ring-shaped electrodes are disposed sequentially and in interval on a side of the first substrate close to the liquid crystal layer. The plurality of second ring-shaped electrodes are disposed sequentially and in interval on a side of the second substrate close to the liquid crystal layer. A plurality of vertical projections, projected by the plurality of first ring-shaped electrodes to the second substrate, and at least partially overlapped with the plurality of second ring-shaped electrodes, respectively.

Abstract: A semiconductor structure includes a ceramic substrate, a first bonding layer, a second bonding layer, a cavity, and a semiconductor layer. The ceramic substrate includes holes on its surface. The first bonding layer is disposed on the surface of the ceramic substrate, and the second bonding layer is bonded to the first bonding layer. The cavity is disposed above the hole and enclosed by the first bonding layer and the second bonding layer. The semiconductor layer extends over the cavity and is disposed along the surface of the second bonding layer.

Abstract: An electronic device includes a substrate, a signal line, a semiconductor, a first conductive portion and a second conductive portion. The signal line is disposed on the substrate. The semiconductor is disposed on the substrate and overlapped with the signal line. Wherein the semiconductor is electrically connected to the first conductive portion and the second conductive portion. Wherein in a top view, at least a portion of the signal line is disposed between the first conductive portion and the second conductive portion. Wherein the first conductive portion has a first curve edge, the second conductive portion has a second curve edge, and the first curve edge and the second curve edge are facing the at least a portion of the signal line and are convex toward the at least a portion of the signal line.

Abstract: A semiconductor device includes a substrate, a buffer layer, a gradient layer, an active layer, a window layer, and an optical filtering layer. The substrate includes a first element and a second element. The buffer layer is disposed on the substrate. The gradient layer is formed on the buffer layer, and includes sublayers. Each sublayer includes the first, second, and third elements. For each sublayer, a lattice constant thereof is adjusted by changing a ratio of the second element to the third element. The active layer is formed on the gradient layer, and includes the first, second, and third elements. The window layer is formed on the active layer. The optical filtering layer includes the first, second, and third elements, and is formed on the window layer to block a portion of light having a wavelength in a predetermined wavelength range.

Abstract: Disclosed is an electronic device including a tunable element, a first power supply circuit, and a second power supply circuit. The first power supply circuit and the second power supply circuit are electrically connected to the tunable element. The first power supply circuit drives the tunable element during a first time period. The second power supply circuit drives the tunable element during a second time period.

Abstract: A method includes forming a transistor layer; forming a first metallization layer, including: forming first conductors, aligned along alpha tracks, and representing input pins of a cell region including first and second input pins; and cutting lengths of the first and second input pins to accommodate at most two access points, each aligned to a different one of first to fourth beta tracks, the beta tracks to which are aligned the access points of the first input pin being different than the beta tracks to which are aligned the access points of the second input pin; and forming a second metallization layer, including: forming second conductors representing routing segments and a representing a power grid segment aligned with one of the beta tracks of access points of the first input pin or the access points of the second input pin.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a conductive gate stack formed over a substrate. A gate dielectric layer covers opposite sidewalls and a bottom of the conductive gate stack. A first gate spacer layer and a second gate spacer layer respectively cover portions of the gate dielectric layer corresponding to the opposite sidewalls of the conductive gate stack. A source/drain contact structure is separated from the conductive gate stack by the gate dielectric layer and the first gate spacer layer. A first insulating capping feature covers the conductive gate stack and is separated from the second gate spacer layer by the gate dielectric layer, and a second insulating capping feature covers the source/drain contact structure. An upper surface of the second insulating capping feature is substantially level with an upper surface of the first insulating capping feature.

Abstract: Techniques for proving haptic feedback in computing systems are described. In operation, an input representing utilisation parameters of an electronic pen is received. In an example, the electronic pen may be electronically coupled to the computing system. Based on the received utilisation parameters, the computing system provides a pattern of haptic feedback to the user.

Abstract: A semiconductor device includes a gate structure on a substrate and an epitaxial layer adjacent to the gate structure, in which the epitaxial layer includes a first buffer layer, an anisotropic layer on the first buffer layer, a second buffer layer on the first buffer layer, and a bulk layer on the anisotropic layer. Preferably, a concentration of boron in the bulk layer is less than a concentration of boron in the anisotropic layer, a concentration of boron in the first buffer layer is less than a concentration of boron in the second buffer layer, and the concentration of boron in the second buffer layer is less than the concentration of boron in the anisotropic layer.

Abstract: An ionic compound, an absorbent and an absorption device are provided. The ionic compound has a structure represented by Formula (I): ABn, ??Formula (I) wherein A is B is R1, R2, R3, R4, R5, and R6 are independently H, C1-6 alkyl group; and n is 1 or 2.

Abstract: A method for forming a memory includes: providing a substrate, a plurality of discrete bit line structures being located on the substrate, and an area surrounded by the adjacent bit line structures and the substrate and having a central axis; forming, on the substrate, a first conductive film filling an area between the adjacent bit line structures; etching the first conductive film by a first etching process to form a first conductive layer; forming a second conductive film on the top surface of the first conductive layer; and etching the second conductive film and the first conductive layer by a second etching process, the remaining second conductive film and the first conductive layer forming a capacitive contact window.