Abstract: In accordance with some embodiments, a package-on-package (PoP) structure includes a first semiconductor package having a first side and a second side opposing the first side, a second semiconductor package having a first side and a second side opposing the first side, and a plurality of inter-package connector coupled between the first side of the first semiconductor package and the first side of the second semiconductor package. The PoP structure further includes a first molding material on the second side of the first semiconductor package. The second side of the second semiconductor package is substantially free of the first molding material.

Abstract: A mobile device includes a system circuit board, a metal frame, one or more other antenna elements, a display device, a first feeding element, and an RF (Radio Frequency) module. The system circuit board includes a system ground plane. The metal frame at least includes a first portion and a second portion. The metal frame at least has a first cut point positioned between the first portion and the second portion. The metal frame further has a second cut point for separating the other antenna elements from the first portion. The first cut point is arranged to be close to a middle region of the display device. The first feeding element is directly or indirectly electrically connected to the first portion. A first antenna structure is formed by the first feeding element and the first portion.

Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.

Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above- mentioned memory device is also provided.

Abstract: A wafer level ultrasonic device includes a composite layer, a first conductive layer, a second conductive layer, a base, a first electrical connection region, and a second electrical connection region. The composite layer includes an ultrasonic element and a protective layer. The ultrasonic element includes a first electrode and a second electrode. The protective layer has a first connecting channel and a second connecting channel respectively corresponding to the first electrode and the second electrode. The first conductive layer and the second conductive layer are respectively in the first connecting channel and the second connecting channel to connect the first electrode and the second electrode. The base includes an opening forming a closed cavity with the protective layer. The first electrical connection region and the second electrical connection region are respectively filled with metal materials to electrically connect the first conductive layer and the second conductive layer.

Abstract: A manufacturing method of a wafer level ultrasonic device includes: forming a first piezoelectric material layer, a first electrode material layer, a second piezoelectric material layer, and a second electrode material layer in sequence on a substrate; removing parts of those layers to form an ultrasonic element including a first electrode and a second electrode; forming a first protective layer on the ultrasonic element, and forming a first through hole and a second through hole exposing a part of the first electrode and a part of the second electrode; forming a first conductive layer and a second conductive layer on the first protective layer and connecting to the first electrode and the second electrode; forming a second protective layer; and connecting a base with an opening and the second protective layer in a vacuum environment to form a closed cavity.

Abstract: A wafer level ultrasonic device includes a composite layer, a first conductive layer, a second conductive layer, a base, a first electrical connection region, and a second electrical connection region. The composite layer includes an ultrasonic element and a protective layer. The ultrasonic element includes a first electrode and a second electrode. The protective layer has a first connecting channel and a second connecting channel respectively corresponding to the first electrode and the second electrode. The first conductive layer and the second conductive layer are respectively in the first connecting channel and the second connecting channel to connect the first electrode and the second electrode. The base includes an opening forming a closed cavity with the protective layer. The first electrical connection region and the second electrical connection region are respectively filled with metal materials to electrically connect the first conductive layer and the second conductive layer.

Abstract: A wafer level ultrasonic chip module includes a substrate, a composite layer, a conducting material, and a base material. The substrate has a through slot that passes through an upper surface of the substrate and a lower surface of the substrate. The composite layer includes an ultrasonic body and a protective layer. A lower surface of the ultrasonic body is exposed from the through slot. The protective layer covers the ultrasonic body and a partial upper surface of the substrate. The protective layer has an opening, from which a partial upper surface of the ultrasonic body is exposed. The conducting material is in contact with the upper surface of the ultrasonic body. The base material covers the through slot, such that a space is formed among the through slot, the lower surface of the ultrasonic body and an upper surface of the base material.

Abstract: A suspended piezoelectric ultrasonic transducer includes a semiconductor substrate and a piezoelectric ultrasonic sensing element. The semiconductor substrate includes a columnar arrangement area, a peripheral wall, and one or more bridge portions. A cavity is between the columnar arrangement area and the peripheral wall. The cavity surrounds the columnar arrangement area, and the bridge portion is connected to the columnar arrangement area and the peripheral wall. The piezoelectric ultrasonic sensing element is disposed on the columnar arrangement area. Through providing the cavity and the bridge portion on the semiconductor substrate, the resonance frequency, the acoustic pressure, and the emitting angle of the transducer can be adjusted, thereby providing a greater manufacturing tolerance for the transducer.

Abstract: A wafer level ultrasonic chip module includes a substrate, a composite layer and a base material. The substrate has a through slot passing through an upper surface and a lower surface of the substrate. The composite layer includes an ultrasonic body and a protective layer. A lower surface of the ultrasonic body is exposed from the through slot. The protective layer covers the ultrasonic body and a partial upper surface of the substrate. The composite layer has a groove passing through an upper surface and a lower surface of the protective layer, and communicating with the through slot. Rhe ultrasonic body corresponds to the through slot. The base material covers the through slot, such that a space is formed among the through slot, the lower surface of the ultrasonic body and an upper surface of the base material.

Abstract: An array-type ultrasonic sensor includes a semiconductor substrate, a first sensing array, and a second sensing array. The first sensing array includes a plurality of first ultrasonic sensing units. Each of the first ultrasonic sensing units includes a first positive electrode and a first negative electrode. The first positive electrodes are connected in series with each other, and the first negative electrodes are connected in series with each other. The second sensing array includes a plurality of second ultrasonic sensing units. Each of the second ultrasonic sensing units includes a second positive electrode and a second negative electrode. The second positive electrodes are connected in series with each other, and the second negative electrodes are connected in series with each other. One of the first sensing array and the second sensing array is configured to transmit ultrasonic waves, and the other is configured to receive reflected ultrasonic waves.

Abstract: A wafer level ultrasonic chip module includes a substrate, a composite layer and a base material. The substrate has a through slot passing through an upper surface and a lower surface of the substrate. The composite layer includes an ultrasonic body and a protective layer. A lower surface of the ultrasonic body is exposed from the through slot. The protective layer covers the ultrasonic body and a partial upper surface of the substrate. The composite layer has a groove passing through an upper surface and a lower surface of the protective layer, and communicating with the through slot. The ultrasonic body corresponds to the through slot. The base material covers the through slot, such that a space is formed among the through slot, the lower surface of the ultrasonic body and an upper surface of the base material.

Abstract: A wafer scale ultrasonic sensor assembly includes a wafer substrate, an ultrasonic element, first and second protective layers, conductive wires, a transmitting material, an ASIC, a conductive bump, and a soldering portion. The wafer substrate includes a via. The ultrasonic element is exposed to the via. The conductive wires are on the first protective layer and connected to the ultrasonic element. The second protective layer covers the conductive wires, and the second protective layer has an opening corresponding to the ultrasonic element. The transmitting material contacts the ultrasonic element. The ASIC is connected to the wafer substrate, so that the via forms a space between the ASIC and the ultrasonic element. The conductive pillar is in a via defined through the ASIC, the wafer substrate, and the first protective layer, and the conducive pillar is respectively connected to the conductive wires and the soldering portion.

Abstract: An array-type ultrasonic sensor includes a semiconductor substrate, a first sensing array, and a second sensing array. The first sensing array includes a plurality of first ultrasonic sensing units. Each of the first ultrasonic sensing units includes a first positive electrode and a first negative electrode. The first positive electrodes are connected in series with each other, and the first negative electrodes are connected in series with each other. The second sensing array includes a plurality of second ultrasonic sensing units. Each of the second ultrasonic sensing units includes a second positive electrode and a second negative electrode. The second positive electrodes are connected in series with each other, and the second negative electrodes are connected in series with each other. One of the first sensing array and the second sensing array is configured to transmit ultrasonic waves, and the other is configured to receive reflected ultrasonic waves.

Abstract: An integrated package method for MEMS element and ASIC chip includes forming a re-layout layer on a front surface of an ASIC wafer; coating an organic compound layer on the re-layout layer and applying a lithography process to the organic compound layer to from a microcavity array; aligning and bonding an electrode connection pad layer on a front surface of an MEMS element with the microcavity array to form a closed cavity structure; thinning and exposing a silicon substrate on a back surface of the MEMS element to a desired thickness; applying the lithographic process on the MEMS element to expose the electrode connection pad layer and an electrical contact area of the re-layout layer; and manufacturing a metal connection member connected to the electrode connection pad layer and the electrical contact area. An integrated package structure for MEMS element and ASIC chip is also provided.

Abstract: A wafer scale ultrasonic sensing device includes a substrate assembly, an ultrasonic component, a first protective layer, a first conductive circuit, a second conductive circuit, a second protective layer, a conductive material, electrical connection layers, and soldering portions. The substrate assembly includes a first wafer and a second wafer, and the second wafer covers a groove on the first wafer to define a hollow chamber. The first wafer, the second wafer, and the first protective layer are coplanar with the first conductive circuit on a first side surface and coplanar with the second conductive circuit on a second side surface. The second protective layer has an opening, where the conductive material is in the opening and is in contact with the ultrasonic component. The electrical connection layers are on the first side surface and the second side surface, and the soldering portions are respectively connected to the electrical connection layers.

Abstract: A wafer level ultrasonic device includes a composite layer, a first conductive layer, a second conductive layer, a base, a first electrical connection region, and a second electrical connection region. The composite layer includes an ultrasonic element and a protective layer. The ultrasonic element includes a first electrode and a second electrode. The protective layer has a first connecting channel and a second connecting channel respectively corresponding to the first electrode and the second electrode. The first conductive layer and the second conductive layer are respectively in the first connecting channel and the second connecting channel to connect the first electrode and the second electrode. The base includes an opening forming a closed cavity with the protective layer. The first electrical connection region and the second electrical connection region are respectively filled with metal materials to electrically connect the first conductive layer and the second conductive layer.

Abstract: A wafer scale ultrasonic sensing device includes a substrate assembly, an ultrasonic component, a first protective layer, a first conductive circuit, a second conductive circuit, a second protective layer, a conductive material, electrical connection layers, and soldering portions. The substrate assembly includes a first wafer and a second wafer, and the second wafer covers a groove on the first wafer to define a hollow chamber. The first wafer, the second wafer, and the first protective layer are coplanar with the first conductive circuit on a first side surface and coplanar with the second conductive circuit on a second side surface. The second protective layer has an opening, where the conductive material is in the opening and is in contact with the ultrasonic component. The electrical connection layers are on the first side surface and the second side surface, and the soldering portions are respectively connected to the electrical connection layers.

Abstract: A light-emitting diode structure includes a substrate, a light-generating structure disposed over the substrate, a first electrode adjacent to a first side of the light-generating structure, a second electrode adjacent to a second side of the light-generating structure opposite to the first side, and a tungsten-doped oxide layer disposed in an electrical conduction path between the light-generating structure and one of the first electrode and the second electrode.

Abstract: An integrated package method for MEMS element and ASIC chip includes forming a re-layout layer on a front surface of an ASIC wafer; coating an organic compound layer on the re-layout layer and applying a lithography process to the organic compound layer to from a microcavity array; aligning and bonding an electrode connection pad layer on a front surface of an MEMS element with the microcavity array to form a closed cavity structure; thinning and exposing a silicon substrate on a back surface of the MEMS element to a desired thickness; applying the lithographic process on the MEMS element to expose the electrode connection pad layer and an electrical contact area of the re-layout layer; and manufacturing a metal connection member connected to the electrode connection pad layer and the electrical contact area. An integrated package structure for MEMS element and ASIC chip is also provided.