Abstract: An antenna structure includes a patch antenna including two opposite edges, a microstrip line connected to the patch antenna, two first radiation assemblies respectively disposed on two sides of the patch antenna, two second radiation assemblies disposed under the two first radiation assemblies, a liquid crystal layer disposed between a first plane and a second plane, and a ground plane disposed under the two second radiation assemblies. The patch antenna, the microstrip line, and the two first radiation assemblies are located on the first plane, and each of the first radiation assemblies includes multiple separated first conductors. The two second radiation assemblies are located on the second plane, and each of the second radiation assemblies includes multiple separated second conductors. A projection of the two second radiation assemblies on the first plane, the two first radiation assemblies, and the two edges of the patch antenna collectively form two loops.

Abstract: A method for measuring a physiological signal includes following steps: detecting a first physiological signal of a target; receiving the first physiological signal to generate a first signal and a second signal by a radar sensor; selecting one of the first signal and the second signal to generate a plurality of original signals, which a phase difference is formed between the first signal and the second signal; and capturing a respiration signal and a heartbeat signal according to the plurality of original signals.

Abstract: An antenna structure includes a patch antenna including two opposite edges, a microstrip line connected to the patch antenna, two first radiation assemblies respectively disposed on two sides of the patch antenna, two second radiation assemblies disposed under the two first radiation assemblies, a liquid crystal layer disposed between a first plane and a second plane, and a ground plane disposed under the two second radiation assemblies. The patch antenna, the microstrip line, and the two first radiation assemblies are located on the first plane, and each of the first radiation assemblies includes multiple separated first conductors. The two second radiation assemblies are located on the second plane, and each of the second radiation assemblies includes multiple separated second conductors. A projection of the two second radiation assemblies on the first plane, the two first radiation assemblies, and the two edges of the patch antenna collectively form two loops.

Abstract: A computer program product, including a non-transitory, computer-readable medium containing instructions therein which, when executed by at least one processor, cause the at least one processor to perform a performance analysis of a network of interconnected nodes, the nodes configured to perform corresponding logic functions. The performance analysis includes, for a pipeline node in the network, calculating a pre-charging finish time of the pipeline node based on an evaluation finish time of a fanout node of the pipeline node and an acknowledge output time parameter of the fanout node. The performance analysis further includes, for the pipeline node in the network, calculating a cycle time of the pipeline node based on the calculated pre-charging finish time and an evaluation finish time of a fanin node of the pipeline node.

Abstract: An antenna unit and an antenna device are provided. The antenna unit comprises a first substrate, a signal line, a first electrode, a second electrode, and an auxiliary electrode. The first substrate has a first surface and a second surface opposite to the first surface. The signal line is located on the first surface of the first substrate. The first electrode is located on the second surface of the first substrate. The first electrode is overlapped with the signal line. The first electrode is ring-shape. The second electrode has a through hole. An accommodating space of the through hole is overlapped with the first electrode. The auxiliary electrode is overlapped with the accommodating space of the through hole and the first electrode.

Abstract: An antenna device includes a first substrate, a first radiation part, a first grounding part, a second radiation part, a liquid crystal layer, and a feeding line. The first substrate includes a first surface and a second surface. The first radiation part is formed on the first surface. The first grounding part includes a slot, and the first radiation part is formed in a projection of the slot projected onto the first surface. The second radiation part is formed in the slot, and coupled with the first grounding part through a conductive segment. The liquid crystal layer is disposed between the first radiation part and the second radiation part. The feeding line is formed on the second surface, and a projection of the first radiation part projected onto the second surface is at least partially overlapping with the feeding line.

Abstract: An antenna unit and an antenna device are provided. The antenna unit comprises a first substrate, a signal line, a first electrode, a second electrode, and an auxiliary electrode. The first substrate has a first surface and a second surface opposite to the first surface. The signal line is located on the first surface of the first substrate. The first electrode is located on the second surface of the first substrate. The first electrode is overlapped with the signal line. The first electrode is ring-shape. The second electrode has a through hole. An accommodating space of the through hole is overlapped with the first electrode. The auxiliary electrode is overlapped with the accommodating space of the through hole and the first electrode.

Abstract: An antenna device includes a first substrate, a first radiation part, a first grounding part, a second radiation part, a liquid crystal layer, and a feeding line. The first substrate includes a first surface and a second surface. The first radiation part is formed on the first surface. The first grounding part includes a slot, and the first radiation part is formed in a projection of the slot projected onto the first surface. The second radiation part is formed in the slot, and coupled with the first grounding part through a conductive segment. The liquid crystal layer is disposed between the first radiation part and the second radiation part. The feeding line is formed on the second surface, and a projection of the first radiation part projected onto the second surface is at least partially overlapping with the feeding line.

Abstract: A computer program product, including a non-transitory, computer-readable medium containing instructions therein which, when executed by at least one processor, cause the at least one processor to perform a performance analysis of a network of interconnected nodes, the nodes configured to perform corresponding logic functions. The performance analysis includes, for a pipeline node in the network, calculating a pre-charging finish time of the pipeline node based on an evaluation finish time of a fanout node of the pipeline node and an acknowledge output time parameter of the fanout node. The performance analysis further includes, for the pipeline node in the network, calculating a cycle time of the pipeline node based on the calculated pre-charging finish time and an evaluation finish time of a fanin node of the pipeline node.

Abstract: A system comprises at least one processor configured to perform technology mapping to map logic elements in a logic netlist to corresponding dual-rail modules in a library. The technology mapping results in a network of interconnected nodes and the mapped dual-rail modules are arranged at corresponding nodes of the network. The processor is configured to optimize the network and perform the technology mapping based on at least one satisfiability-don't-care condition. Performance analysis may be performed by calculating a cycle time of a pipeline node in the network based on a calculated pre-charging finish time and an evaluation finish time of a fanin node of the pipeline node.

Abstract: A display panel includes waveguides, wires and a pixel array. The pixel array includes a plurality of pixel units. The pixel units are arranged in a plurality of columns and a plurality of rows. Each pixel unit includes a pixel electrode, a light filtering unit, and a photo transistor. The light filtering unit is coupled to one of the waveguides. The photo transistor is electrically connected to the pixel electrode and one of the wires, and is coupled to the light filtering unit. The waveguide transmits a light control signal. Each wire transmits an electric control signal. The light filtering unit is configured to receive a sub control signal from the waveguides to which the light filtering unit is coupled and filter out a specific optical signal according to the received sub control signal as an input signal of the photo transistor.

Abstract: A method for providing a logic synthesis of a pipeline circuit is disclosed. The method includes: providing a circuit design of the pipeline circuit, wherein the circuit design includes a first logic module as a current stage, and based on an operation of the first logic module, generating a first time marked graph (TMG) that corresponds to a plurality of behavioral phases of the first logic module, wherein the first TMG includes a plurality of vertexes and a plurality of edges, wherein each vertex corresponds to one of the plurality of behavioral phases that occur in sequence and each edge is coupled between two respective vertexes thereby corresponding to a transition from one behavioral phase to another subsequently occurring behavioral phase.

Abstract: A display panel includes waveguides, wires and a pixel array. The pixel array includes a plurality of pixel units. The pixel units are arranged in a plurality of columns and a plurality of rows. Each pixel unit includes a pixel electrode, a light filtering unit, and a photo transistor. The light filtering unit is coupled to one of the waveguides. The photo transistor is electrically connected to the pixel electrode and one of the wires, and is coupled to the light filtering unit. The waveguide transmits a light control signal. Each wire transmits an electric control signal. The light filtering unit is configured to receive a sub control signal from the waveguides to which the light filtering unit is coupled and filter out a specific optical signal according to the received sub control signal as an input signal of the photo transistor.

Abstract: A method for providing a logic synthesis of a pipeline circuit is disclosed. The method includes: providing a circuit design of the pipeline circuit, wherein the circuit design includes a first logic module as a current stage, and based on an operation of the first logic module, generating a first time marked graph (TMG) that corresponds to a plurality of behavioral phases of the first logic module, wherein the first TMG includes a plurality of vertexes and edges, wherein each vertex corresponds to one of the plurality of behavioral phases that occur in sequence and each edge is coupled between two respective vertexes thereby corresponding to a transition from one behavioral phase to another subsequently occurring behavioral phase.

Abstract: A system comprises at least one processor configured to perform technology mapping to map logic elements in a logic netlist to corresponding dual-rail modules in a library. The technology mapping results in a network of interconnected nodes and the mapped dual-rail modules are arranged at corresponding nodes of the network. The processor is configured to optimize the network and perform the technology mapping based on at least one satisfiability-don't-care condition. Performance analysis may be performed by calculating a cycle time of a pipeline node in the network based on a calculated pre-charging finish time and an evaluation finish time of a fanin node of the pipeline node.

Abstract: A logic circuit includes first and second input, an output, an input acknowledgement node, an output acknowledgement node, a logic evaluation block, a pre-charging circuit, and a completion detection circuit. The logic evaluation block performs a logic evaluation of first and second input signals at the first and second inputs, and to output an output signal corresponding to the logic evaluation. The pre-charging circuit pre-charges the logic evaluation block in response to the first input signal and an acknowledgement signal at the input acknowledgement node. The completion detection circuit generates an acknowledgement signal at the output acknowledgement node in response to the second input signal and the output signal.

Abstract: A display apparatus includes a display panel, a light guide plate, at least one light source and at least one reflective body. The light guide plate is disposed below the display panel. The light guide plate has a light-incident surface, a light-emitting surface, a rear surface, a plurality of concave microstructures and a plurality of reflective bodies. The rear surface is located farther away from the display panel than the light-emitting surface is. The light-incident surface is connected to the light-emitting surface and the rear surface. The concave microstructures are located on the rear surface. The reflective bodies are respectively located in the concave microstructures. The light source is disposed opposite to the light-incident surface.

Abstract: A logic circuit includes first and second input, an output, an input acknowledgement node, an output acknowledgement node, a logic evaluation block, a pre-charging circuit, and a completion detection circuit. The logic evaluation block performs a logic evaluation of first and second input signals at the first and second inputs, and to output an output signal corresponding to the logic evaluation. The pre-charging circuit pre-charges the logic evaluation block in response to the first input signal and an acknowledgement signal at the input acknowledgement node. The completion detection circuit generates an acknowledgement signal at the output acknowledgement node in response to the second input signal and the output signal.

Abstract: A display apparatus includes a display panel, a light guide plate, at least one light source and at least one reflective body. The light guide plate is disposed below the display panel. The light guide plate has a light-incident surface, a light-emitting surface, a rear surface, a plurality of concave microstructures and a plurality of reflective bodies. The rear surface is located farther away from the display panel than the light-emitting surface is. The light-incident surface is connected to the light-emitting surface and the rear surface. The concave microstructures are located on the rear surface. The reflective bodies are respectively located in the concave microstructures. The light source is disposed opposite to the light-incident surface.

Abstract: A display device includes a display module, a cover plate, and a light shielding film. The display module includes a display panel. The display panel has a black matrix pattern that surrounds a display area. The cover plate is configured on the display module. The light shielding film is adhered to at least one of the display module and the cover plate and located between the display module and the cover plate. The light shielding film is substantially located outside the display area, and an inter-medium is configured between the light shielding film and the cover plate and between the display module and the cover plate.