Patents by Inventor Yi-Hsiang Wang

Yi-Hsiang Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12292483
    Abstract: A circuit for parameter PSRR measurement includes a filter, a first regulator and a second regulator. The filter may be configured for receiving an AC input signal and a DC input signal, and for outputting a combined output signal according to the AC input signal and the DC input signal. The first regulator may be configured for receiving the combined output signal, and for outputting a first output signal having a first AC component signal and a first DC component signal. The second regulator may be configured for receiving the first output signal, and for outputting a second output signal having a second AC component signal and a second DC component signal. A parameter PSRR of the second regulator may be obtained according to a ratio between the second AC component signal and the first AC component signal.
    Type: Grant
    Filed: November 23, 2023
    Date of Patent: May 6, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Amit Kundu, Jaw-Juinn Horng, Yi-Hsiang Wang
  • Publication number: 20250110519
    Abstract: The present disclosure provides a low drop-out (LDO) circuit. The LDO circuit includes an input terminal, an output terminal, a cascode operational amplifier, and a power stage. The cascode operational amplifier is electrically connected to the input terminal. The power stage has a first terminal electrically connected to the input terminal, a second terminal electrically connected to an output node of the cascode operational amplifier, and a third terminal electrically connected to the output terminal.
    Type: Application
    Filed: December 12, 2024
    Publication date: April 3, 2025
    Inventor: YI-HSIANG WANG
  • Patent number: 12237133
    Abstract: A overload protection switch with a reverse restart switching structure that has a seesaw lampshade provided with a protruding block which extending downward from the outside of the seesaw lampshade to ensure that the seesaw lampshade and the moving rod are accurately positioned in the ON and OFF positions in the housing to form a three-stage switching type with bidirectional positioning and forms an overload protection switch that can continuously maintain sufficient insulation distance and does not reduce the insulation distance due to fatigue decay of the binary alloy conductive plate.
    Type: Grant
    Filed: September 28, 2023
    Date of Patent: February 25, 2025
    Inventors: Yi-Hsiang Wang, I-Ying Wang
  • Patent number: 12204357
    Abstract: The present disclosure provides a low dropout (LDO) circuit. The LDO circuit includes an input terminal, an output terminal, a cascode operational amplifier, and a power stage. The cascode operational amplifier is electrically connected to the input terminal. The power stage has a first terminal electrically connected to the input terminal, a second terminal electrically connected to an output node of the cascode operational amplifier, and a third terminal electrically connected to the output terminal.
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: January 21, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Yi-Hsiang Wang
  • Publication number: 20240396538
    Abstract: An integrated circuit includes a first conducting line and a second conducting line in a first metal layer above a first transistor and a second transistor. The first conducting line and the second conducting line, which are parallel and adjacent to each other, form a metal-insulator-metal capacitor. Each of the first transistor and the second transistor forms a metal-insulator-semiconductor capacitor. The circuit also includes a third conducting line connected to a source and a drain of the first transistor and configured to receive a first reference voltage. The circuit still includes a fourth conducting line connected to a source and a drain of the second transistor and configured to receive a second reference voltage.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Inventors: Szu-Lin LIU, Jaw-Juinn HORNG, Yi-Hsiang WANG, Wei-Lin LAI
  • Patent number: 12148587
    Abstract: A manufacture method of a concave disc-shaped structure of bimetal strip, particularly to one that is a coaxial positioning method of the guide hole which having elastic disc-shape structure bimetal strips not affected by external stress, which having a bimetal structure which outer edge will not be damaged and does not affect by stress while inner edge pulling closed to the outer edge, it includes: a bimetal strip, a lug, and an assembling jig, having two displaceable positioning holes, and use the guiding surface to make the two positioning holes gradually turn inside to condense to the combining surface of the lugs, so as to achieve the purpose of accurate positioning and combination.
    Type: Grant
    Filed: October 27, 2021
    Date of Patent: November 19, 2024
    Inventors: Yi-Hsiang Wang, I-Ying Wang
  • Patent number: 12101091
    Abstract: A method includes fabricating a first transistor and a second transistor on a substrate and fabricating a first conducting line and a second conducting line in a first metal layer. The method also includes connecting a gate of the first transistor to the first conducting line and connecting a gate of the second transistor to the second conducting line. The first conducting line and the second conducting line are parallel and adjacent to each other in the first metal layer above the first transistor and the second transistor. The method still includes connecting a source and a drain of the first transistor to a third conducting line.
    Type: Grant
    Filed: April 25, 2023
    Date of Patent: September 24, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Szu-Lin Liu, Jaw-Juinn Horng, Yi-Hsiang Wang, Wei-Lin Lai
  • Publication number: 20240297261
    Abstract: A semiconductor device includes a substrate, a buffer layer, a gradient layer, an active layer, a window layer, and an optical filtering layer. The substrate includes a first element and a second element. The buffer layer is disposed on the substrate. The gradient layer is formed on the buffer layer, and includes sublayers. Each sublayer includes the first, second, and third elements. For each sublayer, a lattice constant thereof is adjusted by changing a ratio of the second element to the third element. The active layer is formed on the gradient layer, and includes the first, second, and third elements. The window layer is formed on the active layer. The optical filtering layer includes the first, second, and third elements, and is formed on the window layer to block a portion of light having a wavelength in a predetermined wavelength range.
    Type: Application
    Filed: March 1, 2024
    Publication date: September 5, 2024
    Inventors: Hung-Wen HUANG, Yung-Chao CHEN, Yi-Hsiang WANG, Wei LIN
  • Publication number: 20240162356
    Abstract: A light detecting device includes a substrate that has a lattice constant. A buffer layer is disposed on the substrate. A gradient layer is formed on the buffer layer opposite to the substrate, and includes a plurality of sublayers that have respectively lattice constants each of which is greater than the lattice constant of the substrate. The sublayers are arranged in a manner that the lattice constants of the sublayers undergo a gradual increase in lattice constant in a direction away from the substrate. A barrier layer is formed on the gradient layer opposite to the buffer layer, and has a lattice constant which is greater than that of the substrate and no smaller than the lattice constants of the sublayers. An absorption layer is formed on the barrier layer opposite to the gradient layer.
    Type: Application
    Filed: March 29, 2023
    Publication date: May 16, 2024
    Inventors: Hung-Wen HUANG, Yung-Chao CHEN, Yi-Hsiang WANG, Wei LIN
  • Publication number: 20240112874
    Abstract: A overload protection switch with a reverse restart switching structure that has a seesaw lampshade provided with a protruding block which extending downward from the outside of the seesaw lampshade to ensure that the seesaw lampshade and the moving rod are accurately positioned in the ON and OFF positions in the housing to form a three-stage switching type with bidirectional positioning and forms an overload protection switch that can continuously maintain sufficient insulation distance and does not reduce the insulation distance due to fatigue decay of the binary alloy conductive plate.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 4, 2024
    Inventors: YI-HSIANG WANG, I-YING WANG
  • Publication number: 20240085491
    Abstract: A circuit for parameter PSRR measurement includes a filter, a first regulator and a second regulator. The filter may be configured for receiving an AC input signal and a DC input signal, and for outputting a combined output signal according to the AC input signal and the DC input signal. The first regulator may be configured for receiving the combined output signal, and for outputting a first output signal having a first AC component signal and a first DC component signal. The second regulator may be configured for receiving the first output signal, and for outputting a second output signal having a second AC component signal and a second DC component signal. A parameter PSRR of the second regulator may be obtained according to a ratio between the second AC component signal and the first AC component signal.
    Type: Application
    Filed: November 23, 2023
    Publication date: March 14, 2024
    Inventors: AMIT KUNDU, JAW-JUINN HORNG, YI-HSIANG WANG
  • Patent number: 11860238
    Abstract: A circuit for parameter PSRR measurement includes a filter, a first regulator and a second regulator. The filter may be configured for receiving an AC input signal and a DC input signal, and for outputting a combined output signal according to the AC input signal and the DC input signal. The first regulator may be configured for receiving the combined output signal, and for outputting a first output signal having a first AC component signal and a first DC component signal. The second regulator may be configured for receiving the first output signal, and for outputting a second output signal having a second AC component signal and a second DC component signal. A parameter PSRR of the second regulator may be obtained according to a ratio between the second AC component signal and the first AC component signal.
    Type: Grant
    Filed: February 16, 2022
    Date of Patent: January 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Amit Kundu, Jaw-Juinn Horng, Yi-Hsiang Wang
  • Patent number: 11853092
    Abstract: A device is provided. The device includes an operational amplifier, an output circuit, a first capacitor, and a second capacitor. The operational amplifier is configured to generate an output according to a feedback signal. The output circuit is configured to generate a first current signal in response to a supply voltage and the output of the operational amplifier. The first current signal includes a first ripple signal. The first capacitor and the second capacitor are coupled in parallel between the operational amplifier and the output circuit. The first capacitor is configured to receive the first current signal and feedback to the operational amplifier the first ripple signal.
    Type: Grant
    Filed: February 6, 2023
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Hsiang Wang, Jaw-Juinn Horng
  • Publication number: 20230343785
    Abstract: A method of manufacturing an integrated circuit (IC) device includes forming a metal oxide semiconductor (MOS) transistor including a first gate and first and second source/drain (S/D) regions, the first and second S/D regions having a first doping type and being formed in a substrate region having a second doping type different from the first doping type, forming a guard ring structure surrounding the MOS transistor, the guard ring structure including a second gate and first and second heavily doped regions, the first and second heavily doped regions being formed in the substrate region and having the second doping type, and constructing a first electrical connection between the first and second gates.
    Type: Application
    Filed: June 28, 2023
    Publication date: October 26, 2023
    Inventors: Yi-Hsiang WANG, Szu-Lin LIU, Jaw-Juinn HORNG, Yung-Chow PENG
  • Publication number: 20230288947
    Abstract: The present disclosure provides a low dropout (LDO) circuit. The LDO circuit includes an input terminal, an output terminal, a cascode operational amplifier, and a power stage. The cascode operational amplifier is electrically connected to the input terminal. The power stage has a first terminal electrically connected to the input terminal, a second terminal electrically connected to an output node of the cascode operational amplifier, and a third terminal electrically connected to the output terminal.
    Type: Application
    Filed: March 10, 2022
    Publication date: September 14, 2023
    Inventor: YI-HSIANG WANG
  • Publication number: 20230268911
    Abstract: A method includes fabricating a first transistor and a second transistor on a substrate and fabricating a first conducting line and a second conducting line in a first metal layer. The method also includes connecting a gate of the first transistor to the first conducting line and connecting a gate of the second transistor to the second conducting line. The first conducting line and the second conducting line are parallel and adjacent to each other in the first metal layer above the first transistor and the second transistor. The method still includes connecting a source and a drain of the first transistor to a third conducting line.
    Type: Application
    Filed: April 25, 2023
    Publication date: August 24, 2023
    Inventors: Szu-Lin LIU, Jaw-Juinn HORNG, Yi-Hsiang WANG, Wei-Lin LAI
  • Publication number: 20230231554
    Abstract: A method (of decoupling from voltage variations in a first voltage drop between first and second reference voltage rails) includes: electrically coupling one or more components to form a decoupling capacitance (decap) circuit; electrically coupling one or more components to form a filtered biasing circuit; and making an unswitched series electrical coupling of the decap circuit and the filtered biasing circuit between the first and second reference voltage rails.
    Type: Application
    Filed: March 13, 2023
    Publication date: July 20, 2023
    Inventors: Szu-Lin LIU, Yi-Hsiang WANG, Jaw-Juinn HORNG
  • Patent number: 11699771
    Abstract: A non-diffusion type photodiode is described and has: a substrate, a buffer layer, a light absorption layer, an intermediate layer, and a multiplication/window layer. The buffer layer is disposed on the substrate. The light absorption layer is disposed on the buffer layer. The intermediate layer is disposed on the light absorption layer and has a first boundary, wherein the intermediate layer is an I-type semiconductor layer or a graded refractive index layer. The multiplication/window layer is disposed on the intermediate layer and has a second boundary, wherein in a top view, the first boundary surrounds the second boundary, and a distance between the first boundary and the second boundary is greater than or equal to 1 micrometer. The non-diffusion type photodiode can reduce generation of dark current.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: July 11, 2023
    Assignee: LANDMARK OPTOELECTRONICS CORPORATION
    Inventors: Huang-wei Pan, Hung-Wen Huang, Yung-Chao Chen, Yi-Hsiang Wang
  • Patent number: 11695007
    Abstract: A method of biasing a guard ring structure includes biasing a gate of a MOS transistor to a first bias voltage level, biasing first and second S/D regions of the MOS transistor to a power domain voltage level, biasing a gate of the guard ring structure to a second bias voltage level, and biasing first and second heavily doped regions of the guard ring structure to the power domain voltage level. Each of the first and second S/D regions has a first doping type, each of the first and second heavily doped regions has a second doping type different from the first doping type, and each of the first and second S/D regions and the first and second heavily doped regions is positioned in a substrate region having the second doping type.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: July 4, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Hsiang Wang, Szu-Lin Liu, Jaw-Juinn Horng, Yung-Chow Peng
  • Patent number: D1053155
    Type: Grant
    Filed: January 18, 2023
    Date of Patent: December 3, 2024
    Inventors: Yi-Hsiang Wang, I-Ying Wang