Abstract: A clock data recovery apparatus includes an oscillator, a sampler circuit, and a frequency control circuit. The oscillator generates a clock signal according to a bias voltage. The sampler circuit samples an input data signal to generate a sampling signal according to the clock signal. The frequency control circuit generates the bias voltage by performing integration calculation, digital-to-analog conversion, and low-pass filtering for the sampling signal.

Abstract: A clock data recovery apparatus includes an oscillator, a sampler circuit, and a frequency control circuit. The oscillator generates a clock signal according to a bias voltage. The sampler circuit samples an input data signal to generate a sampling signal according to the clock signal. The frequency control circuit generates the bias voltage by performing integration calculation, digital-to-analog conversion, and low-pass filtering for the sampling signal.

Abstract: An interpolator includes interpolation cells. Each interpolation cell includes a first driving unit and a second driving unit. The first driving unit includes a first pulling-up circuit for selectively coupling an output terminal to a high voltage, a first pulling-down circuit for selectively coupling the output terminal to a low voltage, and a pair of first switches for selectively enabling/disabling the first pulling-up circuit and the first pulling-down circuit. The second driving unit includes a second pulling-up circuit for selectively coupling the output terminal to the high voltage, a second pulling-down circuit for selectively coupling the output terminal to the low voltage, and a pair of second switches for selectively enabling/disabling the second pulling-up circuit and the second pulling-down circuit. Driving capabilities of the first and second pulling-up circuits are not all equal, and/or driving capabilities of the first and second pulling-down circuits are not all equal.

Abstract: A method of estimating gain of a time-to-digital converter (TDC) includes: capturing a TDC output sample; calculating a gradient in response to the TDC output sample; and adjusting a TDC normalizing gain based on the calculating step. Another method of calibrating gain of a TDC includes: capturing a phase error which is derived from a TDC output sample, a reference phase and a variable phase; calculating a gradient in response to the phase error; and adjusting a TDC normalizing gain based on the calculating step.

Abstract: A time-to-digital system, such as a frequency synthesizer, includes a power management circuit and a time-to-digital converter (TDC). Said power management circuit is coupled to a frequency reference clock and a variable clock, and arranged to output a delayed frequency reference clock and a single pulse of said variable clock ahead of a transition of said delayed frequency reference clock. Said TDC is coupled to said power management circuit and arranged to produce a digital TDC output.

Abstract: An interpolator includes interpolation cells. Each interpolation cell includes a first driving unit and a second driving unit. The first driving unit includes a first pulling-up circuit for selectively coupling an output terminal to a high voltage, a first pulling-down circuit for selectively coupling the output terminal to a low voltage, and a pair of first switches for selectively enabling/disabling the first pulling-up circuit and the first pulling-down circuit. The second driving unit includes a second pulling-up circuit for selectively coupling the output terminal to the high voltage, a second pulling-down circuit for selectively coupling the output terminal to the low voltage, and a pair of second switches for selectively enabling/disabling the second pulling-up circuit and the second pulling-down circuit. Driving capabilities of the first and second pulling-up circuits are not all equal, and/or driving capabilities of the first and second pulling-down circuits are not all equal.

Abstract: A phase/frequency detector for controlling a charge pump includes: a core circuit arranged to output a first phase signal and a second phase signal according to a phase/frequency difference between a reference clock signal and an input clock signal; and a timing circuit coupled to the core circuit and arranged to generate a first control signal and a second control signal for controlling the charge pump according to the first phase signal and the second phase signal, wherein only one of the first control signal and the second control signal is indicative of an enabled operation when the reference clock signal and the input clock signal are substantially identical in phase.

Abstract: A frequency synthesizer includes an oscillator for providing an RF clock, a phase shifter arranged to provide a shifted reference clock by changing phase of a frequency reference clock, and a time-to-digital converter (TDC) for producing a digital TDC output by quantizing a time difference between said RF clock and said shifted reference clock; wherein a range of said TDC covers significantly less than a full range of said RF clock period. An associated method is also provided.

Abstract: A method of estimating mismatches of a time-to-digital converter (TDC) includes: capturing phase error samples; calculating difference between the phase error samples and an expected value of the phase error samples; and adjusting correction gain of the TDC based on the calculating step. Another method of estimating mismatches of a TDC includes: capturing TDC output code samples; storing a plurality of accumulation values corresponding to different TDC values respectively, wherein each accumulation value records a number of times a TDC value is carried by the TDC output code samples; calculating a desired value based on the accumulation values; calculating difference between the accumulation values and the desired value; and adjusting correction gain of the TDC based on the calculating step.

Abstract: A frequency synthesizer includes an oscillator for providing an RF clock, a phase shifter coupled to said oscillator for providing a shifted RF clock by changing phase of said RF clock, and a time-to-digital converter (TDC) coupled to said phase shifter for quantizing a time difference between a frequency reference clock and said shifted RF clock, wherein a range of said TDC covers significantly less than a full range of said RF clock period. An associated method is also provided.

Abstract: A method of estimating mismatches of a time-to-digital converter (TDC) includes: capturing phase error samples; calculating difference between the phase error samples and an expected value of the phase error samples; and adjusting correction gain of the TDC based on the calculating step. Another method of estimating mismatches of a TDC includes: capturing TDC output code samples; storing a plurality of accumulation values corresponding to different TDC values respectively, wherein each accumulation value records a number of times a TDC value is carried by the TDC output code samples; calculating a desired value based on the accumulation values; calculating difference between the accumulation values and the desired value; and adjusting correction gain of the TDC based on the calculating step.

Abstract: A method of estimating gain of a time-to-digital converter (TDC) includes: capturing a TDC output sample; calculating a gradient in response to the TDC output sample; and adjusting a TDC normalizing gain based on the calculating step. Another method of calibrating gain of a TDC includes: capturing a phase error which is derived from a TDC output sample, a reference phase and a variable phase; calculating a gradient in response to the phase error; and adjusting a TDC normalizing gain based on the calculating step.

Abstract: The frequency calibration device includes a logic unit for gating the clock signal according to a gating window signal to generate a gated clock signal, and a divider for dividing the gated clock signal by a divisor in frequency to generate a frequency indication signal, and output digits of the divider are set to the divisor in a calibration cycle, and the frequency indication signal is a most significant bit of the output digits.

Abstract: A time-to-digital system, such as a frequency synthesizer, includes a power management circuit and a time-to-digital converter (TDC). Said power management circuit is coupled to a frequency reference clock and a variable clock, and arranged to output a delayed frequency reference clock and a single pulse of said variable clock ahead of a transition of said delayed frequency reference clock. Said TDC is coupled to said power management circuit and arranged to produce a digital TDC output.

Abstract: A frequency synthesizer includes an oscillator for providing an RF clock, a phase shifter arranged to provide a shifted reference clock by changing phase of a frequency reference clock, and a time-to-digital converter (TDC) for producing a digital TDC output by quantizing a time difference between said RF clock and said shifted reference clock; wherein a range of said TDC covers significantly less than a full range of said RF clock period. An associated method is also provided.

Abstract: A frequency synthesizer includes an oscillator for providing an RF clock, a phase shifter coupled to said oscillator for providing a shifted RF clock by changing phase of said RF clock, and a time-to-digital converter (TDC) coupled to said phase shifter for quantizing a time difference between a frequency reference clock and said shifted RF clock, wherein a range of said TDC covers significantly less than a full range of said RF clock period. An associated method is also provided.

Abstract: A charge pump being disposed in a phase locking system. The charge pump includes a sourcing element, a draining element and an offset element. The sourcing element is arranged to selectively source a first current into an output terminal of the charge pump according to a first control signal, and the draining element is arranged to selectively drain a second current from the output terminal according to a second control signal. The offset element is arranged to selectively conduct an offset current via the output terminal according to a third control signal, and one of the sourcing element and the draining element is disabled when the phase locking system is in a phase-locked state.

Abstract: A charge pump being disposed in a phase locking system. The charge pump includes a sourcing element, a draining element and an offset element. The sourcing element is arranged to selectively source a first current into an output terminal of the charge pump according to a first control signal, and the draining element is arranged to selectively drain a second current from the output terminal according to a second control signal. The offset element is arranged to selectively conduct an offset current via the output terminal according to a third control signal, and one of the sourcing element and the draining element is disabled when the phase locking system is in a phase-locked state.

Abstract: The present invention applies management frame defined in IEEE 802.11 standard to a wireless distribution system (WDS) mode by adding an information element (IE) into the management frame, which enables any access point (AP) in WDS to maintain IE based on its own setting and state, then send IE via the management frame for providing state of the AP under WDS mode, determine whether a physical link (i.e., a wireless link between APs) should be established therewith based on received IE, and maintain the established physical link through the wireless management frame in a real time manner. Thus, the existence and necessity of the physical link between different APs in WDS can be determined correctly.

Abstract: The frequency calibration device includes a logic unit for gating the clock signal according to a gating window signal to generate a gated clock signal, and a divider for dividing the gated clock signal by a divisor in frequency to generate a frequency indication signal, and output digits of the divider are set to the divisor in a calibration cycle, and the frequency indication signal is a most significant bit of the output digits.