Patents by Inventor Yi-Hsien Lee

Yi-Hsien Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190189614
    Abstract: A method includes forming a first fin on a semiconductor substrate, forming an isolation dielectric material over the first fin, and planarizing the isolation dielectric material. A top surface of the first fin is covered by the isolation dielectric material after planarizing the isolation dielectric material. The method further includes etching back the isolation dielectric material until the first fin protrudes from the isolation dielectric material.
    Type: Application
    Filed: February 11, 2019
    Publication date: June 20, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Juei LEE, Chia-Ming LIANG, Chi-Hsin CHANG, Jin-Aun NG, Yi-Shien MOR, Huai-Hsien CHIU
  • Publication number: 20180012963
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a substrate; a fin structure protruding from the substrate, the fin structure extending along a first direction; isolation features disposed on both sides of the fin structure; a gate structure over the fin structure and extending on the isolation features along a second direction perpendicular to the first direction; and wherein the gate structure includes a first segment and a second segment, the second segment being over the first segment and including a greater dimension in the first direction than that of the first segment.
    Type: Application
    Filed: September 12, 2017
    Publication date: January 11, 2018
    Inventors: CHENG-TA WU, YI-HSIEN LEE, WEI-MING YOU, TING-CHUN WANG
  • Patent number: 9768261
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a substrate; a fin structure protruding from the substrate, the fin structure extending along a first direction; isolation features disposed on both sides of the fin structure; a gate structure over the fin structure and extending on the isolation features along a second direction perpendicular to the first direction; and wherein the gate structure includes a first segment and a second segment, the second segment being over the first segment and including a greater dimension in the first direction than that of the first segment.
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: September 19, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Cheng-Ta Wu, Yi-Hsien Lee, Wei-Ming You, Ting-Chun Wang
  • Patent number: 9637839
    Abstract: Aromatic molecules are seeded on a surface of a growth substrate; and a layer (e.g., a monolayer) of a metal dichalcogenide is grown via chemical vapor deposition on the growth substrate surface seeded with aromatic molecules. The seeded aromatic molecules are contacted with a solvent that releases the metal dichalcogenide layer from the growth substrate. The metal dichalcogenide layer can be released with an adhered transfer medium and can be deposited on a target substrate.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: May 2, 2017
    Assignee: Massachusetts Institute of Technology
    Inventors: Jing Kong, Lain-Jong Li, Yi-Hsien Lee
  • Publication number: 20160308059
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a substrate; a fin structure protruding from the substrate, the fin structure extending along a first direction; isolation features disposed on both sides of the fin structure; a gate structure over the fin structure and extending on the isolation features along a second direction perpendicular to the first direction; and wherein the gate structure includes a first segment and a second segment, the second segment being over the first segment and including a greater dimension in the first direction than that of the first segment.
    Type: Application
    Filed: April 17, 2015
    Publication date: October 20, 2016
    Inventors: CHENG-TA WU, YI-HSIEN LEE, WEI-MING YOU, TING-CHUN WANG
  • Publication number: 20150102713
    Abstract: A casing for receiving a hard disk drive includes a top wall, a bottom wall, two sidewalls, and an end wall. A number of metal bars protrude from an inner surface of the top wall.
    Type: Application
    Filed: October 31, 2013
    Publication date: April 16, 2015
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Chih-Hao LIN, Yi-Hsien LEE
  • Publication number: 20150064471
    Abstract: A metal dichalcogenide layer is produced on a transfer substrate by seeding F16CuPc molecules on a surface of a growth substrate, growing a layer (e.g., a monolayer) of a metal dichalcogenide via chemical vapor deposition on the growth substrate surface seeded with F16CuPc molecules, and contacting the F16CuPc-molecule and metal-dichalcogenide coated growth substrate with a composition that releases the metal dichalcogenide from the growth substrate.
    Type: Application
    Filed: August 27, 2014
    Publication date: March 5, 2015
    Inventors: Mildred S. Dresselhaus, Jing Kong, Yi-Hsien Lee, Xi Ling
  • Publication number: 20150047822
    Abstract: A heat sink is configured to dissipate heat generated by an electronic component and protect the electronic component from Electromagnetic Interference (EMI). The heat sink comprises a base and a number of waveguides extending out from the base. A number of through holes is defined through the base. Each of the waveguides is a hollow but blind tube communicating with a through hole.
    Type: Application
    Filed: August 18, 2014
    Publication date: February 19, 2015
    Inventors: CHIH-HAO LIN, YI-HSIEN LEE
  • Publication number: 20140245946
    Abstract: Aromatic molecules are seeded on a surface of a growth substrate; and a layer (e.g., a monolayer) of a metal dichalcogenide is grown via chemical vapor deposition on the growth substrate surface seeded with aromatic molecules. The seeded aromatic molecules are contacted with a solvent that releases the metal dichalcogenide layer from the growth substrate. The metal dichalcogenide layer can be released with an adhered transfer medium and can be deposited on a target substrate.
    Type: Application
    Filed: February 28, 2014
    Publication date: September 4, 2014
    Applicant: Massachusetts Institute of Technology
    Inventors: Jing Kong, Lain-Jong Li, Yi-Hsien Lee
  • Patent number: 7800391
    Abstract: An apparatus and method for testing an integrated circuit in a target electronic application, wherein the apparatus includes a socket for receiving the integrated circuit, a modified commercial electronic product which models the target electronic application, and an electrical connection between the socket and the modified commercial electronic product. The method of testing an integrated circuit includes placing an integrated circuit in a socket that is coupled to a circuit board substantially identical to that of a circuit board configured to include the integrated circuit, but which does not include the integrated circuit, and testing the integrated circuit. A method of making such a tester mechanically attaching a socket to a modified commercial electronic product and electrically connecting an integrated circuit and the modified commercial electronic product. This approach allows for cheaper, more comprehensive, and more accurate testing of an integrated circuit.
    Type: Grant
    Filed: June 23, 2006
    Date of Patent: September 21, 2010
    Assignee: MediaTek Inc.
    Inventors: Tai-Hung Lin, Chih-Ming Chiang, Yi-Hsien Lee, Chi-Ming Lee
  • Publication number: 20070164771
    Abstract: An apparatus and method for testing an integrated circuit in a target electronic application, wherein the apparatus comprises a socket for receiving the integrated circuit, a modified commercial electronic product which models the target electronic application, and an electrical connection between the socket and the modified commercial electronic product. The method of testing an integrated circuit comprises placing an integrated circuit in a socket that is coupled to a circuit board substantially identical to that of a circuit board configured to include the integrated circuit, but which does not include the integrated circuit, and testing the integrated circuit. A method of making such a tester mechanically attaching a socket to a modified commercial electronic product and electrically connencting an integrated circuit and the modified commercial electronic product. This approach allows for cheaper, more comprehensive, and more accurate testing of an integrated circuit.
    Type: Application
    Filed: June 23, 2006
    Publication date: July 19, 2007
    Inventors: Tai-Hung Lin, Chih-Ming Chiang, Yi-Hsien Lee, Chi-Ming Lee
  • Publication number: 20040012556
    Abstract: A method and device for controlling the illumination of a backlight of an LCD includes a light sensor that generates an ambient light intensity value, a processor that interprets the measured ambient light intensity value, a light source that is controlled by the processor, and an LCD device that is illuminated by the light source. The processor first calculates a light source intensity value based on a user-adjustable desired apparent light source brightness value and the measured ambient light intensity value. The processor then triggers the light source to emit light at a time-averaged intensity, utilizing frequency variation or a varying duty cycle, which corresponds to the calculated light source intensity value, such that the LCD device is illuminated. In this way, the information displayed on the LCD is clearly visible to a user in any ambient lighting condition.
    Type: Application
    Filed: July 17, 2002
    Publication date: January 22, 2004
    Inventors: Sea-Weng Yong, Chih-Chiang Huang, Yi-Hsien Lee
  • Patent number: 5761479
    Abstract: A single chip replacement upgradeable/downgradeable data processing system capable of operating with different types of central processing unit (CPU) chips. The system has a first socket for registration of a first CPU chip and a second socket for registration of a second CPU chip. Circuitry is provided for preventing possible signal contention between the first and second CPU chips and for synchronizing clocks for operating a CPU with the system clock. Circuitry is also provided for interfacing with a coprocessor associated with the different types of CPU chips as well as for adjusting the signals to and from the CPU chips to the signal width of the system.
    Type: Grant
    Filed: March 31, 1995
    Date of Patent: June 2, 1998
    Assignee: Acer Incorporated
    Inventors: Hung-Ta Huang, Te-Chih Chuang, Yunn-Hung Liao, Yi-Hsien Lee, Lung Wei
  • Patent number: 5551012
    Abstract: An upgradeable/downgradeable computer system is made capable of being driven by more than one model of central processing units, including at least one socket means capable of being plugged with different model of central processing units, an identifying circuit capable of identifying the model of the central processing unit in the socket means and generating an identifying signal, a clock generator responsive to the identifying signal for generating a clock signal acceptable to the model of the central processing unit in the socket means, and a means responsive to the identifying signal for gating and inhibiting a plurality of input/output signals of the central processing unit in the socket means.
    Type: Grant
    Filed: March 8, 1994
    Date of Patent: August 27, 1996
    Assignee: Acer Incorporated
    Inventors: Te-Chih Chuang, Yunn-Hung Liao, Lung Wei, Yi-Hsien Lee