Patents by Inventor Yi-Hsien Lu
Yi-Hsien Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11963295Abstract: Provided are a circuit apparatus, a manufacturing method thereof, and a circuit system. The circuit apparatus includes a flexible circuit board, a flexible packaging material layer and an electronic device. The flexible circuit board has at least one hollow pattern, wherein the flexible circuit board has an inner region and a peripheral region surrounding the inner region, and has a first surface and a second surface opposite to each other. The flexible packaging material layer is disposed in the at least one hollow pattern. The electronic device is disposed on the first surface of the flexible circuit board and electrically connected with the flexible circuit board.Type: GrantFiled: January 27, 2022Date of Patent: April 16, 2024Assignee: Industrial Technology Research InstituteInventors: Hung-Hsien Ko, Yi-Cheng Lu, Heng-Yin Chen, Hao-Wei Yu, Te-Hsun Lin
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Publication number: 20240092662Abstract: A method for removing a heavy metal from water includes subjecting a microbial solution containing a liquid culture of a urease-producing bacterial strain and a reaction solution containing a manganese compound and urea to a microbial-induced precipitation reaction, so as to obtain biomineralized manganese carbonate (MnCO3) particles, admixing the biomineralized MnCO3 particles with water containing a heavy metal, so that the biomineralized MnCO3 particles adsorb the heavy metal in the water to form a precipitate, and removing the precipitate from the water.Type: ApplicationFiled: February 9, 2023Publication date: March 21, 2024Inventors: Chien-Yen CHEN, Yi-Hsun HUANG, Pin-Yun LIN, Anggraeni Kumala DEWI, Koyeli DAS, Uttara SUKUL, Tsung-Hsien CHEN, Raju Kumar SHARMA, Cheng-Kang LU, Chung-Ming LU
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Publication number: 20240071656Abstract: A circuit protection device includes a first temperature sensitive resistor, a second temperature sensitive resistor, an electrically insulating multilayer, a first and second electrode layer, and at least one external electrode. The first temperature sensitive resistor and the second temperature sensitive resistor are electrically connected in parallel, and have a first upper electrically conductive layer and a second lower electrically conductive layer, respectively. The electrically insulating multilayer includes an upper insulating layer, a middle insulating layer, and a lower insulating layer. The upper insulating layer is between the first upper electrically conductive layer and the first electrode layer. The middle layer is laminated between the first temperature sensitive resistor and the second temperature sensitive resistor. The lower insulating layer is between the second lower electrically conductive layer and the second electrode layer.Type: ApplicationFiled: January 13, 2023Publication date: February 29, 2024Inventors: Chien Hui WU, Yung-Hsien CHANG, Cheng-Yu TUNG, Ming-Hsun LU, Yi-An SHA
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Patent number: 11821081Abstract: This disclosure provides systems, methods, and apparatus related to thin free-standing oxide membranes. In one aspect, a method includes providing a substrate. The substrate defines a hole having a diameter of about 500 nanometers to 5000 nanometers. A layer of metal is deposited on the substrate. A supporting layer is deposited on the layer of metal. A first side of the supporting layer is the side that is disposed on the layer of metal. A metal oxide layer is deposited on the first side of the supporting layer and on the substrate. In some implementations, the method further includes removing the supporting layer.Type: GrantFiled: October 4, 2021Date of Patent: November 21, 2023Assignee: The Regents of the University of CaliforniaInventors: Yi-Hsien Lu, Xiao Zhao, Matthijs van Spronsen, Adam Schwartzberg, Miquel Salmeron, Carlos Morales Sanchez
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Patent number: 11672124Abstract: The present disclosure relates to an integrated circuit that includes a semiconductor substrate having a periphery region and memory cell region separated by a boundary region. A pair of split gate flash memory cells are disposed on the memory cell region and include a first select gate and a first memory gate. A first gate electrode is disposed over a first gate dielectric layer on the periphery region. A second gate electrode is disposed over a second gate dielectric layer on the periphery region at a position between the boundary region and the first gate electrode. The second dielectric layer is thicker than the first gate dielectric layer. The first select gate and the first memory gate have upper surfaces that are co-planar or level with the upper surface of the second gate electrode.Type: GrantFiled: February 25, 2021Date of Patent: June 6, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Harry-Hak-Lay Chuang, Wei Cheng Wu, Ya-Chen Kao, Yi Hsien Lu
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Publication number: 20220359552Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.Type: ApplicationFiled: July 26, 2022Publication date: November 10, 2022Inventors: Chen-Chin LIU, Wei Cheng WU, Yi Hsien LU, Yu-Hsiung WANG, Juo-Li YANG
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Patent number: 11430799Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.Type: GrantFiled: September 30, 2019Date of Patent: August 30, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chen-Chin Liu, Wei Cheng Wu, Yi Hsien Lu, Yu-Hsiung Wang, Juo-Li Yang
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Publication number: 20220112596Abstract: This disclosure provides systems, methods, and apparatus related to thin free-standing oxide membranes. In one aspect, a method includes providing a substrate. The substrate defines a hole having a diameter of about 500 nanometers to 5000 nanometers. A layer of metal is deposited on the substrate. A supporting layer is deposited on the layer of metal. A first side of the supporting layer is the side that is disposed on the layer of metal. A metal oxide layer is deposited on the first side of the supporting layer and on the substrate. In some implementations, the method further includes removing the supporting layer.Type: ApplicationFiled: October 4, 2021Publication date: April 14, 2022Inventors: Yi-Hsien Lu, Xiao Zhao, Matthijs van Spronsen, Adam Schwartzberg, Miquel Salmeron, Carlos Morales Sanchez
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Publication number: 20210183880Abstract: The present disclosure relates to an integrated circuit that includes a semiconductor substrate having a periphery region and memory cell region separated by a boundary region. A pair of split gate flash memory cells are disposed on the memory cell region and include a first select gate and a first memory gate. A first gate electrode is disposed over a first gate dielectric layer on the periphery region. A second gate electrode is disposed over a second gate dielectric layer on the periphery region at a position between the boundary region and the first gate electrode. The second dielectric layer is thicker than the first gate dielectric layer. The first select gate and the first memory gate have upper surfaces that are co-planar or level with the upper surface of the second gate electrode.Type: ApplicationFiled: February 25, 2021Publication date: June 17, 2021Inventors: Harry-Hak-Lay Chuang, Wei Cheng Wu, Ya-Chen Kao, Yi Hsien Lu
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Patent number: 10957704Abstract: The present disclosure relates to a structure and method for embedding a non-volatile memory (NVM) in a HKMG (high-? metal gate) integrated circuit which includes a high-voltage (HV) HKMG transistor. NVM devices (e.g., flash memory) are operated at high voltages for its read and write operations and hence a HV device is necessary for integrated circuits involving non-volatile embedded memory and HKMG logic circuits. Forming a HV HKMG circuit along with the HKMG periphery circuit reduces the need for additional boundaries between the HV transistor and rest of the periphery circuit. This method further helps reduce divot issue and reduce cell size.Type: GrantFiled: January 6, 2020Date of Patent: March 23, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Harry-Hak-Lay Chuang, Wei Cheng Wu, Ya-Chen Kao, Yi Hsien Lu
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Publication number: 20200373317Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.Type: ApplicationFiled: August 10, 2020Publication date: November 26, 2020Inventors: Chen-Chin LIU, Wei Cheng WU, Yi Hsien LU, Yu-Hsiung WANG, Juo-Li YANG
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Patent number: 10741569Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.Type: GrantFiled: October 4, 2017Date of Patent: August 11, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chen-Chin Liu, Wei Cheng Wu, Yi Hsien Lu, Yu-Hsiung Wang, Juo-Li Yang
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Patent number: 10672778Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.Type: GrantFiled: October 4, 2017Date of Patent: June 2, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chen-Chin Liu, Wei Cheng Wu, Yi Hsien Lu, Yu-Hsiung Wang, Juo-Li Yang
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Publication number: 20200144279Abstract: The present disclosure relates to a structure and method for embedding a non-volatile memory (NVM) in a HKMG (high-? metal gate) integrated circuit which includes a high-voltage (HV) HKMG transistor. NVM devices (e.g., flash memory) are operated at high voltages for its read and write operations and hence a HV device is necessary for integrated circuits involving non-volatile embedded memory and HKMG logic circuits. Forming a HV HKMG circuit along with the HKMG periphery circuit reduces the need for additional boundaries between the HV transistor and rest of the periphery circuit. This method further helps reduce divot issue and reduce cell size.Type: ApplicationFiled: January 6, 2020Publication date: May 7, 2020Inventors: Harry-Hak-Lay Chuang, Wei Cheng Wu, Ya-Chen Kao, Yi Hsien Lu
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Publication number: 20200027889Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.Type: ApplicationFiled: September 30, 2019Publication date: January 23, 2020Inventors: Chen-Chin LIU, Wei Cheng WU, Yi Hsien LU, Yu-Hsiung WANG, Juo-Li YANG
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Patent number: 10535675Abstract: The present disclosure relates to a structure and method for embedding a non-volatile memory (NVM) in a HKMG (high-? metal gate) integrated circuit which includes a high-voltage (HV) HKMG transistor. NVM devices (e.g., flash memory) are operated at high voltages for its read and write operations and hence a HV device is necessary for integrated circuits involving non-volatile embedded memory and HKMG logic circuits. Forming a HV HKMG circuit along with the HKMG periphery circuit reduces the need for additional boundaries between the HV transistor and rest of the periphery circuit. This method further helps reduce divot issue and reduce cell size.Type: GrantFiled: April 29, 2019Date of Patent: January 14, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Harry-Hak-Lay Chuang, Wei Cheng Wu, Ya-Chen Kao, Yi Hsien Lu
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Publication number: 20190252400Abstract: The present disclosure relates to a structure and method for embedding a non-volatile memory (NVM) in a HKMG (high-? metal gate) integrated circuit which includes a high-voltage (HV) HKMG transistor. NVM devices (e.g., flash memory) are operated at high voltages for its read and write operations and hence a HV device is necessary for integrated circuits involving non-volatile embedded memory and HKMG logic circuits. Forming a HV HKMG circuit along with the HKMG periphery circuit reduces the need for additional boundaries between the HV transistor and rest of the periphery circuit. This method further helps reduce divot issue and reduce cell size.Type: ApplicationFiled: April 29, 2019Publication date: August 15, 2019Inventors: Harry-Hak-Lay Chuang, Wei Cheng Wu, Ya-Chen Kao, Yi Hsien Lu
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Patent number: 10276588Abstract: The present disclosure relates to a structure and method for embedding a non-volatile memory (NVM) in a HKMG (high-? metal gate) integrated circuit which includes a high-voltage (HV) HKMG transistor. NVM devices (e.g., flash memory) are operated at high voltages for its read and write operations and hence a HV device is necessary for integrated circuits involving non-volatile embedded memory and HKMG logic circuits. Forming a HV HKMG circuit along with the HKMG periphery circuit reduces the need for additional boundaries between the HV transistor and rest of the periphery circuit. This method further helps reduce divot issue and reduce cell size.Type: GrantFiled: May 1, 2017Date of Patent: April 30, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Harry-Hak-Lay Chuang, Wei Cheng Wu, Ya-Chen Kao, Yi Hsien Lu
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Publication number: 20190006380Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.Type: ApplicationFiled: October 4, 2017Publication date: January 3, 2019Inventors: Chen-Chin LIU, Wei Cheng WU, Yi Hsien LU, Yu-Hsiung WANG, Juo-Li YANG
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Publication number: 20170236833Abstract: The present disclosure relates to a structure and method for embedding a non-volatile memory (NVM) in a HKMG (high-? metal gate) integrated circuit which includes a high-voltage (HV) HKMG transistor. NVM devices (e.g., flash memory) are operated at high voltages for its read and write operations and hence a HV device is necessary for integrated circuits involving non-volatile embedded memory and HKMG logic circuits. Forming a HV HKMG circuit along with the HKMG periphery circuit reduces the need for additional boundaries between the HV transistor and rest of the periphery circuit. This method further helps reduce divot issue and reduce cell size.Type: ApplicationFiled: May 1, 2017Publication date: August 17, 2017Inventors: Harry-Hak-Lay Chuang, Wei Cheng Wu, Ya-Chen Kao, Yi Hsien Lu