Patents by Inventor Yi-Hsin Ko
Yi-Hsin Ko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11916151Abstract: Present disclosure provides a semiconductor structure, including a semiconductor fin having a first portion and a second portion over the first portion, a first conductive region abutting a first lateral surface of the first portion and a first lateral surface of the second portion, a metal gate having a bottom portion and an upper portion, the bottom portion being between the first portion and the second portion of the semiconductor fin, and the upper portion being over the second portion of the semiconductor fin, and a first spacer between the bottom portion of the metal gate and the first conductive region. A method for manufacturing the semiconductor structure described herein is also provided.Type: GrantFiled: June 25, 2021Date of Patent: February 27, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chia-Ming Hsu, Yi-Jing Li, Chih-Hsin Ko, Kuang-Hsin Chen, Da-Wen Lin, Clement Hsingjen Wann
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Publication number: 20230401371Abstract: A method of designing a semiconductor device including the operations of analyzing a vertical abutment between a first standard cell block and a second cell block and, if a mismatch is identified between the first standard cell block and the second cell block initiating the selection of a first modified cell block that reduces the mismatch and a spacing between the first modified cell block and the second cell block, the first modified cell block comprising a first abutment region having a continuous active region arranged along a first axis parallel to an edge of the vertical abutment, and replacing the first standard cell block with the first modified cell block to obtain a first modified layout design and devices manufactured according to the method.Type: ApplicationFiled: August 9, 2023Publication date: December 14, 2023Inventors: Chi-Yu LU, Hui-Zhong ZHUANG, Pin-Dai SUE, Yi-Hsin KO, Li-Chun TIEN
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Publication number: 20230334208Abstract: The present disclosure describes a method for optimizing metal cuts in standard cells. The method includes placing a standard cell in a layout area and inserting a metal cut along a metal interconnect of the standard cell at a location away from a boundary of the standard cell. The method further includes disconnecting, at the location, a metal portion of the metal interconnect from a remaining portion of the metal interconnect based on the metal cut.Type: ApplicationFiled: June 26, 2023Publication date: October 19, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheok-Kei LEI, Zhe-Wei JIANG, Chi-Yu LU, Yi-Hsin KO, Chi-Lin LIU, Hui-Zhong ZHUANG
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Patent number: 11768989Abstract: A method of designing a semiconductor device including the operations of analyzing a vertical abutment between a first standard cell block and a second cell block and, if a mismatch is identified between the first standard cell block and the second cell block initiating the selection of a first modified cell block that reduces the mismatch and a spacing between the first modified cell block and the second cell block, the first modified cell block comprising a first abutment region having a continuous active region arranged along a first axis parallel to an edge of the vertical abutment, and replacing the first standard cell block with the first modified cell block to obtain a first modified layout design and devices manufactured according to the method.Type: GrantFiled: December 21, 2021Date of Patent: September 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chi-Yu Lu, Hui-Zhong Zhuang, Pin-Dai Sue, Yi-Hsin Ko, Li-Chun Tien
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Patent number: 11734481Abstract: The present disclosure describes a method for optimizing metal cuts in standard cells. The method includes placing a standard cell in a layout area and inserting a metal cut along a metal interconnect of the standard cell at a location away from a boundary of the standard cell. The method further includes disconnecting, at the location, a metal portion of the metal interconnect from a remaining portion of the metal interconnect based on the metal cut.Type: GrantFiled: May 17, 2021Date of Patent: August 22, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheok-Kei Lei, Chi-Lin Liu, Hui-Zhong Zhuang, Zhe-Wei Jiang, Chi-Yu Lu, Yi-Hsin Ko
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Publication number: 20220114322Abstract: A method of designing a semiconductor device including the operations of analyzing a vertical abutment between a first standard cell block and a second cell block and, if a mismatch is identified between the first standard cell block and the second cell block initiating the selection of a first modified cell block that reduces the mismatch and a spacing between the first modified cell block and the second cell block, the first modified cell block comprising a first abutment region having a continuous active region arranged along a first axis parallel to an edge of the vertical abutment, and replacing the first standard cell block with the first modified cell block to obtain a first modified layout design and devices manufactured according to the method.Type: ApplicationFiled: December 21, 2021Publication date: April 14, 2022Inventors: Chi-Yu LU, Hui-Zhong ZHUANG, Pin-Dai SUE, Yi-Hsin KO, Li-Chun TIEN
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Patent number: 11216608Abstract: A semiconductor device comprising at least one modified cell block that includes a modified abutment region in which is provided a first continuous active region arranged along a first axis parallel to a vertical abutment edge for positioning adjacent other cell blocks to form a vertical abutment, including non-standard, standard, and modified cell blocks. The structure provided within the modified abutment region improves a structural and device density match between the modified cell block and the adjacent cell block, thereby reducing the need for white space between vertically adjacent cell blocks and reducing the total device area and increasing cell density.Type: GrantFiled: October 25, 2019Date of Patent: January 4, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chi-Yu Lu, Hui-Zhong Zhuang, Li-Chun Tien, Pin-Dai Sue, Yi-Hsin Ko
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Publication number: 20210271794Abstract: The present disclosure describes a method for optimizing metal cuts in standard cells. The method includes placing a standard cell in a layout area and inserting a metal cut along a metal interconnect of the standard cell at a location away from a boundary of the standard cell. The method further includes disconnecting, at the location, a metal portion of the metal interconnect from a remaining portion of the metal interconnect based on the metal cut.Type: ApplicationFiled: May 17, 2021Publication date: September 2, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheok-Kei Lei, Chi-Lin Liu, Hui-Zhong Zhuang, Zhe-Wei Jiang, Chi-Yu Lu, Yi-Hsin Ko
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Patent number: 11030368Abstract: The present disclosure describes a method for optimizing metal cuts in standard cells. The method includes placing a standard cell in an layout area and inserting a metal cut along a metal interconnect of the standard cell at a location away from a boundary of the standard cell. The method further includes disconnecting, at the location, a metal portion of the metal interconnect from a remaining portion of the metal interconnect based on the metal cut.Type: GrantFiled: May 22, 2020Date of Patent: June 8, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheok-Kei Lei, Chi-Lin Liu, Hui-Zhong Zhuang, Zhe-Wei Jiang, Chi-Yu Lu, Yi-Hsin Ko
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Publication number: 20200285792Abstract: The present disclosure describes a method for optimizing metal cuts in standard cells. The method includes placing a standard cell in an layout area and inserting a metal cut along a metal interconnect of the standard cell at a location away from a boundary of the standard cell. The method further includes disconnecting, at the location, a metal portion of the metal interconnect from a remaining portion of the metal interconnect based on the metal cut.Type: ApplicationFiled: May 22, 2020Publication date: September 10, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheok-Kei LEI, Chi-Lin LIU, Hui-Zhong ZHUANG, Zhe-Wei JIANG, Chi-Yu LU, Yi-Hsin KO
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Patent number: 10691849Abstract: The present disclosure describes a method for optimizing metal cuts in standard cells. The method includes placing a standard cell in an layout area and inserting a metal cut along a metal interconnect of the standard cell at a location away from a boundary of the standard cell. The method further includes disconnecting, at the location, a metal portion of the metal interconnect from a remaining portion of the metal interconnect based on the metal cut.Type: GrantFiled: February 28, 2018Date of Patent: June 23, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheok-Kei Lei, Chi-Lin Liu, Hui-Zhong Zhuang, Zhe-Wei Jiang, Chi-Yu Lu, Yi-Hsin Ko
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Publication number: 20200134126Abstract: A semiconductor device comprising at least one modified cell block that includes a modified abutment region in which is provided a first continuous active region arranged along a first axis parallel to a vertical abutment edge for positioning adjacent other cell blocks to form a vertical abutment, including non-standard, standard, and modified cell blocks. The structure provided within the modified abutment region improves a structural and device density match between the modified cell block and the adjacent cell block, thereby reducing the need for white space between vertically adjacent cell blocks and reducing the total device area and increasing cell density.Type: ApplicationFiled: October 25, 2019Publication date: April 30, 2020Inventors: Chi-Yu LU, Hui-Zhong ZHUANG, Li-Chun TIEN, Pin-Dai SUE, Yi-Hsin KO
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Publication number: 20190095552Abstract: The present disclosure describes a method for optimizing metal cuts in standard cells. The method includes placing a standard cell in an layout area and inserting a metal cut along a metal interconnect of the standard cell at a location away from a boundary of the standard cell. The method further includes disconnecting, at the location, a metal portion of the metal interconnect from a remaining portion of the metal interconnect based on the metal cut.Type: ApplicationFiled: February 28, 2018Publication date: March 28, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheok-Kei LEI, Chi-Lin Liu, Hui-Zhong Zhuang, Zhe-Wei Jiang, Chi-Yu Lu, Yi-Hsin Ko