Patents by Inventor Yi-Hsin Lin

Yi-Hsin Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250144150
    Abstract: The present invention provides a preparation method of pharmaceutical composition for treating chronic stroke, involving injection via brain into the cranium of a patient having chronic stroke for six months or more; the pharmaceutical composition is a suspension at least comprising adipose-derived stem cells treated by cell expansion, an active synergistic component and a growth factor, wherein the expression level of CD34 and CD45 of the adipose-derived stem cells treated by cell expansion is 10% or less, and the expression level of CD90 and CD105 is 90% or more; the active synergistic component is an extracellular vesicle; the growth factor is at least one selected from the group consisting of HGF, G-CSF, Fractalkine, IP-10, EGF, IL-1?, IL-1?, IL-4, IL-5, IL-13, IFN?, TGF? and sCD40L. The present invention overcomes the limitations of previous cell therapy and provides a cell-based preparation that is clinically safe and therapeutically effective for chronic cerebral stroke.
    Type: Application
    Filed: January 8, 2025
    Publication date: May 8, 2025
    Inventors: Po-Cheng Lin, Pi-Chun Huang, Chia-Hsin Lee, Ming-Hsi Chuang, Chun-Hung Chen, Chao-Liang Chang, Kai-Ling Zhang, Yi-Chun Lin, Yu-Chen Tsai, Peggy Leh Jiunn Wong, Ruei-Yue Liang
  • Publication number: 20250151381
    Abstract: The present disclosure describes a semiconductor device having fin structures with optimized fin pitches for substantially uniform S/D structures. The semiconductor device includes multiple fin structures on a substrate. The multiple fin structures have a first pitch and a second pitch in an alternate configuration and the second pitch is different from the first pitch. The semiconductor device further includes a gate structure on the multiple fin structures and a source/drain (S/D) structure adjacent to the gate structure and in contact with the multiple fin structures.
    Type: Application
    Filed: November 3, 2023
    Publication date: May 8, 2025
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hung LIN, Wei Hsin LIN, Hui-Hsuan KUNG, Yi-Lii HUANG
  • Publication number: 20250138676
    Abstract: An electronic device including a display panel and a CPU is provided. The display panel updates displayed images at a refresh rate. The CPU implements a latency monitor, a system resource controller, a display controller, and an application. The latency monitor collects time information related to touch latency. The touch latency is the duration between the time point at which the display panel detects a touch event and the time point at which the display panel displays an image generated by the application in response to said touch event. The display controller informs the system resource controller of the refresh rate. The system resource controller adjusts the resource allocation of the electronic device to cause the touch latency to be lower than a threshold, according to the time information and the refresh rate.
    Type: Application
    Filed: October 25, 2024
    Publication date: May 1, 2025
    Inventors: Yi-Hsin SHEN, Nien-Hsien LIN, Yen-Po CHIEN, Yen-An SHIH, Chiu-Jen LIN, Cheng-Che CHEN
  • Patent number: 12287566
    Abstract: An optical system is provided and includes a first optical element driving mechanism, which includes a first fixed assembly, a first movable assembly, and a first driving assembly. The first movable assembly is configured to be connected to a first optical element, and the first movable assembly is movable relative to the first fixed assembly. The first movable assembly includes a first movable element and a second movable element. The first driving assembly is configured to drive the first movable assembly to move relative to the first fixed assembly. The first fixed assembly and the first movable assembly are arranged along a main axis, and the first driving assembly is configured to drive the second movable element to move along a first axis, thereby driving the first movable element to move around the main axis.
    Type: Grant
    Filed: October 6, 2022
    Date of Patent: April 29, 2025
    Assignee: TDK TAIWAN CORP.
    Inventors: Chan-Jung Hsu, Chen-Hsin Huang, Chen-Hung Chao, Yi-Ho Chen, Kun-Shih Lin, Shou-Jen Liu
  • Publication number: 20250132355
    Abstract: A flow battery stack is provided with carbon-felt electrodes etched with canals. The stack comprises carbon-felt electrodes, bipolar plates, separating membranes, and electrolytes. A plurality of canals are etched on the surface of the electrode to increase the flow rate of electrolyte for improving reactivity. With the carbon-felt electrodes used in the flow battery stack, a long-term and stable charging/discharging operation is achieved with the cost of electricity storage effectively reduced.
    Type: Application
    Filed: April 1, 2024
    Publication date: April 24, 2025
    Inventors: Chien-Hong Lin, Yi-Hsin Hu, Ning-Yih Hsu, Hwa-Jou Wei
  • Publication number: 20250118632
    Abstract: A memory device may comprise a substrate, a plurality of memory cells, and a header device. The substrate may have a first side and a second side opposite to each other. The plurality of memory cells may be formed on the first side of the substrate. The header device may be formed on the first side of the substrate. The header device can be configured to selectively couple a supply voltage through a first combination of power delivery paths or a second combination of power delivery paths to the plurality of memory cells based on a control signal.
    Type: Application
    Filed: October 10, 2023
    Publication date: April 10, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Hsin Nien, Chih-Yu Lin, Hidehiro Fujiwara, Yen-Huei Chen
  • Publication number: 20250117227
    Abstract: A method for adjusting application settings is provided. The method includes using an application setting module to receive at least one performance target from an application running on an electronic device. The method further includes using the application setting module to record at least one performance indicator of the application while the application is running, wherein the performance indicator corresponds to the performance target. The method further includes using the application setting module to estimate the estimated time that the temperature of the electronic device sustains less than the defense temperature. The method further includes using the application setting module to determine the score according to the performance indicator and the estimated time, wherein the score indicates to the application that it should raise, lower, or keep a current setting.
    Type: Application
    Filed: April 25, 2024
    Publication date: April 10, 2025
    Inventors: Ching-Yeh CHEN, Yi-Wei HO, Te-Hsin LIN, Shih-Ting HUANG, Chung Hao HO, Yu-Hsien LIN, Chiu-Jen LIN, Cheng-Che CHEN
  • Publication number: 20250112052
    Abstract: Disclosed herein are methods for forming opening ends within semiconductor structures. In some embodiments, a method may include providing an opening formed in a layer of a semiconductor device, wherein the opening comprises a set of sidewalls opposite one another, and first and second end walls connected to the sidewalls, wherein each of the first and second end walls defines a tip end and a set of curved sections extending between the tip end and the set of sidewall. The method may further include performing an ion etch to the opening by delivering an ion beam at a non-zero angle relative to a plane defined by the layer of the semiconductor device, wherein the ion etch comprises a lean-gas chemistry, and wherein the ion etch causes the layer of the semiconductor device to be removed faster along the set of curved sections than along the set of sidewalls.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicant: Applied Materials, Inc.
    Inventors: Yi-Hsin CHEN, Kevin R. Anglin, Yong Yang, Solomon Belangedi Basame, Yung-Chen Lin, Gang Shu
  • Patent number: 12260903
    Abstract: A memory array is disclosed. The memory array includes a plurality of memory cells disposed over a substrate. Each of the memory cells is coupled to a corresponding one of a plurality of word lines and a corresponding one of a plurality of bit line pairs. First four of the memory cells that are coupled to four consecutive ones of the word lines and to a first one of the bit line pairs are abutted to one another on the substrate along a single lateral direction.
    Type: Grant
    Filed: July 12, 2022
    Date of Patent: March 25, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Hsin Nien, Hidehiro Fujiwara, Chih-Yu Lin, Yen-Huei Chen
  • Publication number: 20250098226
    Abstract: Present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor fin and a metal gate. The semiconductor fin has a first portion and a second portion over the first portion. A height of the second portion is greater than a width of the second portion. The metal gate has a bottom portion, an upper portion, and a lateral portion connecting the bottom portion and the upper portion. The bottom portion is between the first portion and the second portion of the semiconductor fin, and the upper portion is over the second portion of the semiconductor fin.
    Type: Application
    Filed: December 5, 2024
    Publication date: March 20, 2025
    Inventors: CHIA-MING HSU, YI-JING LI, CHIH-HSIN KO, KUANG-HSIN CHEN, DA-WEN LIN, CLEMENT HSINGJEN WANN
  • Publication number: 20250098254
    Abstract: The present disclosure provides a semiconductor device and a method of forming the same. A method according to one embodiment includes forming a plurality of fins protruding from a substrate, forming first and second dummy gate stacks over the fins, and depositing a cover structure over the fins. A first portion of the cover structure extends between the first and second dummy gate stacks. The method also includes etching the fins to form a first trench between the first dummy gate stack and the first portion of the cover structure and a second trench between the second dummy gate stack and the first portion of the cover structure, removing the cover structure, epitaxially growing a first epitaxial feature from the first trench and a second epitaxial feature from the second trench. The first and second epitaxial features merge after rising above a top surface of the fins.
    Type: Application
    Filed: January 25, 2024
    Publication date: March 20, 2025
    Inventors: Hou-Hsueh Wu, Wei Hsin Lin, Hui-Hsuan Kung, Yi-Lii Huang, Chih-Hsiao Chen
  • Patent number: 12248173
    Abstract: Disclosed is an optical module, including a lower housing, an upper housing covering the lower housing, a circuit board, a first metal base, a second metal base, a silicon photonic chip, and a light emission module including a laser chip and an optical path assembly. The first metal base is disposed on one side of the upper housing. The second metal base is disposed on one side of the lower housing. The circuit board with a hollow region is disposed on the second metal base. The silicon photonic chip is disposed on the second metal base exposed from the hollow region. The laser chip is disposed on the first metal base. The optical path assembly is disposed on the first metal base and/or on the second metal base exposed from the hollow region, and guides a third optical signal emitted by the laser chip to the silicon photonic chip.
    Type: Grant
    Filed: December 22, 2022
    Date of Patent: March 11, 2025
    Assignee: DONGGUAN LUXSHARE TECHNOLOGIES CO., LTD
    Inventors: Chung-Hsin Fu, Min-Sheng Kao, ChunFu Wu, Yi-Tseng Lin, Chih-Wei Yu, Chien-Tzu Wu, QianBing Yan, Yueh-Kuo Lin
  • Patent number: 12242313
    Abstract: A system determines a current state of an information handling system, and receives a sensor output signal. The system determines whether a status change of the sensor output signal relates to an expected state based on the current state and a previous state of the information handling system, and determines whether the sensor output signal is triggered by an external magnet. If the status change of the sensor output signal relates to the expected state and the sensor output signal is not triggered by the external magnet, then the system transitions the information handling system from the current state to the expected state.
    Type: Grant
    Filed: September 28, 2023
    Date of Patent: March 4, 2025
    Assignee: Dell Products L.P.
    Inventors: Chen Hsin Chang, Wan Shih Chien, Yi Min Lin
  • Patent number: 12234396
    Abstract: An optical adhesive film structure having an alignment function is provided. The optical adhesive film structure includes an optical adhesive layer and a release film. The release film is disposed on the optical adhesive layer. A first film surface of the release film facing away from the optical adhesive layer has a plurality of marks. The marks are recessed into the release film relative to the first film surface and do not run through the release film. A stitching display module and a manufacturing method of the stitching display module are also provided.
    Type: Grant
    Filed: December 8, 2022
    Date of Patent: February 25, 2025
    Assignee: AUO CORPORATION
    Inventors: Yi-Hsin Lin, Wen-Lung Chen, Yu-Chin Wu, Wei-Lung Liau
  • Publication number: 20250061838
    Abstract: An electronic device is provided. The electronic device includes a display panel and a controller coupled to the display panel. The display panel is configured to update displayed images at a refresh rate. The controller is configured to receive a target frame rate from a first application. The controller is further configured to determine a frame rate according to the refresh rate and the target frame rate. The frame rate is a factor of the refresh rate. The controller is further configured to control the first application to draw images at the frame rate.
    Type: Application
    Filed: August 15, 2024
    Publication date: February 20, 2025
    Inventors: Yi-Hsin SHEN, Cheng-Che CHEN, Yen-Po CHIEN, Chung-Hao HO, Jen-Chih CHANG, Chiu-Jen LIN
  • Publication number: 20250057841
    Abstract: The present invention relates methods for treating thyroid cancer, renal cell carcinoma or hepatocellar carcinoma comprising orally administering to a patient in need of such therapy a therapeutic amount of cabozantinib lauryl sulfate salt, preferably in a capsule form. The method allows the administration of the therapeutic amount of cabozantinib lauryl sulfate salt in a fed state or a fasted state and the administration does not exhibit a food effect.
    Type: Application
    Filed: October 30, 2024
    Publication date: February 20, 2025
    Applicant: Handa Oncology, LLC
    Inventors: Fang-Yu Liu, K.C. Sung, Chin-Yao Yang, Chi-Cheng Lin, Yi-Hsin Lin, Li Qiao
  • Publication number: 20250063709
    Abstract: A method (of manufacturing a memory device) includes forming active regions extending in a first direction; over the active regions, doing as follows including, forming gate structures extending in a second direction perpendicular to the first direction, and forming contact-to-source/drain structures (MD structures) which extend in the second direction and are interspersed among corresponding ones of the gate structures; forming via-to-gate/MD (VGD) structures over corresponding ones of the gate structures and the MD structures; in a first metallization layer over the VGD structures, forming first front-side segments extending in the first direction and including one or more front-side routing (FRTE) segments; under the active regions, forming buried segment-to-source/drain structures (BVD structures); and in a first buried metallization layer under the BVD structures, forming first back-side segments extending in the first direction and including one or more first back-side power grid (BPG) segments.
    Type: Application
    Filed: November 5, 2024
    Publication date: February 20, 2025
    Inventors: Hidehiro FUJIWARA, Chih-Yu LIN, Yen-Huei CHEN, Wei-Chang ZHAO, Yi-Hsin NIEN
  • Patent number: 12230318
    Abstract: A memory device includes a first word line and a second word line. A first portion of the first word line is formed in a first metal layer, a second portion of the first word line is formed in a second metal layer above the first metal layer, and a third portion of the first word line is formed in a third metal layer below the second metal layer. A first portion of the second word line is formed in the first metal layer. A second portion of the second word line is formed in the second metal layer. The first portion, the second portion, and the third portion of the first word line have sizes that are different from each other, and the first portion and the second portion of the second word line have sizes that are different from each other.
    Type: Grant
    Filed: July 22, 2022
    Date of Patent: February 18, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Hsin Nien, Wei-Chang Zhao, Chih-Yu Lin, Hidehiro Fujiwara, Yen-Huei Chen, Ru-Yu Wang
  • Publication number: 20250049797
    Abstract: The present invention relates methods for treating thyroid cancer, renal cell carcinoma or hepatocellar carcinoma comprising orally administering to a patient in need of such therapy a therapeutic amount of cabozantinib lauryl sulfate salt, preferably in a capsule form. The method allows the administration of the therapeutic amount of cabozantinib lauryl sulfate salt in a fed state or a fasted state and the administration does not exhibit a food effect.
    Type: Application
    Filed: October 30, 2024
    Publication date: February 13, 2025
    Applicant: Handa Oncology, LLC
    Inventors: Fang-Yu Liu, K.C. Sung, Chin-Yao Yang, Chi-Cheng Lin, Yi-Hsin Lin, Li Qiao
  • Publication number: 20250044636
    Abstract: An optical system includes a pancake lens assembly and a varifocal lens device. The varifocal lens device is coupled to the pancake lens assembly in a way that an optical axis of the varifocal lens device is in alignment with an optical axis of the pancake lens assembly, thereby permitting the optical system to have an adjustable focal length.
    Type: Application
    Filed: October 21, 2024
    Publication date: February 6, 2025
    Inventors: Yi-hsin Lin, Ting-Wei Huang, Yu-Jen Wang