Abstract: A memory device includes a first memory array comprising first memory cells; a second memory array comprising second memory cells; a third memory array comprising third memory cells, the second memory array interposed between the first memory array and the third memory array along a lateral direction; a first bit line segment extending along the lateral direction and coupled to each of the first memory cells; a second bit line segment extending along the lateral direction and coupled to each of the second memory cells; and a third bit line segment extending along the lateral direction and coupled to each of the third memory cells. The first bit line segment is formed in a first metallization layer, the second bit line segment is formed in a second metallization layer, and the third bit line segment is formed in a third metallization layer.

Abstract: Present disclosure provides a method including: forming a semiconductor stack having at least one SiGe layer; forming a plurality of fins from the semiconductor stack by a first etching operation, each of the plurality of fins comprising a first portion and a second portion over the first portion, the first portion being separated from the second portion by a SiGe portion; forming a poly gate stripe orthogonally over the plurality of fins; forming a recess on each of the plurality of fins abutting the poly gate; recessing the SiGe portion by a second etching operation through the recess; forming a first spacer and a second spacer to surround the SiGe portion; and removing the SiGe portion.

Abstract: A method, a processing device, and a system for information display are provided, and the system includes a light transmissive display. A first information extraction device extracts spatial position information of a user, and a second information extraction device extracts spatial position information of a target object. The processing device performs the following steps. Display position information of virtual information of the target object on the display is determined according to the spatial position information of the user and the spatial position information of the target object. The display position information includes a first display reference position corresponding to a previous time and a second display reference position corresponding to a current time. An actual display position of the virtual information on the display corresponding to the current time is determined according to a distance between the first display reference position and the second display reference position.

Abstract: A semiconductor device includes a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell operatively arranged along a first one of a plurality of columns, and operatively arranged in a first one, a second one, a third one, and a fourth one of a plurality of rows, respectively. The first column operatively corresponds to a first pair of bit lines and a second pair of bit lines. The first to fourth rows operatively correspond to a first word line, a second word line, a third word line, and a fourth word line, respectively. The first pair of bit lines are operatively coupled to the first and second memory cells. The second pair of bit lines are operatively coupled to the third and fourth memory cells.

Abstract: A semiconductor manufacturing apparatus for performing a process is disclosed. An apparatus includes a chamber configured to receive a wafer for an etching process; a conductive focus ring disposed within the chamber and configured to focus an electric field to control an etch direction of the etching process; and an insulative cover ring disposed within the chamber, wherein the insulative cover ring is configured to modify the electric field, wherein the insulative cover ring has an inner annular insulative portion and outer annular insulative portion, and wherein a gap is defined between the inner annular insulative portion and the outer annular insulative portion.

Abstract: A memory device includes a conductive segment, first and second rows of memory cells. The conductive segment receives a first reference voltage signal. The first row of memory cells is coupled to a first word line. The second row of memory cells is coupled to a second word line. The first row of memory cells includes first and second memory cells. The first memory cell is coupled to the conductive segment to receive the first reference voltage signal. The second row of memory cells includes third and fourth memory cells. The third memory cell is coupled to the conductive segment to receive the first reference voltage signal. The first and third memory cells share the conductive segment, and the third memory cell is arranged between the first and second memory cells. The second memory cell is arranged between the third and fourth memory cells.

Abstract: An optical element driving mechanism is provided. The optical element driving mechanism includes a movable portion for holding an optical element, a fixed portion, a driving assembly used for driving the movable portion to move relative to the fixed portion, and an adhesive element. The movable portion is movable relative to the fixed portion, and the fixed portion includes a case and a bottom affixed on the case. The case has a top wall and a side wall. The top wall is plate-shaped and is perpendicular to a main axis, and the side wall is not parallel to the top wall. An accommodating space for accommodating the movable portion is formed between the case and the bottom. The adhesive element is in direct contact with the bottom, the case, and the driving assembly.

Abstract: A display panel includes a circuit substrate, a first supporting structure, a glue layer residue and light-emitting diodes. The circuit substrate has electrodes. The first supporting structure is located outside the electrodes on the circuit substrate. The glue layer residue is located on the first supporting structure. The light-emitting diodes are electrically connected to the electrodes.

Abstract: The present invention relates methods for treating chronic myeloid leukemia and/or lymphoblastic leukemia by orally administering to a patient in need of such a therapeutic amount of dasatinib lauryl sulfate salt, preferably in a tablet, capsule or suspension form. The method allows the administration of the therapeutic amount of dasatinib lauryl sulfate salt a fed state or a fasted state and the administration does not exhibit a food effect.

Abstract: Disclosed are a co-packaged integrated optoelectronic module and a co-packaged optoelectronic switch chip. The co-packaged integrated optoelectronic module includes a carrier board, and an optoelectronic submodule, a slave microprocessor and a master microprocessor disposed on and electrically connected to the carrier board. In the optoelectronic submodule, a digital signal processing chip converts an electrical analog signal into an electrical digital signal, an optoelectronic signal analog conversion chip converts an optical analog signal into the electrical analog signal to the digital signal processing chip, and an optical transceiver chip receives and transmits the optical analog signal to the optoelectronic signal analog conversion chip. The slave microprocessor monitors operation of the optoelectronic submodule.

Abstract: A memory device includes active regions and gate structures, each of the gate structures is electrically coupled to a first portion of a corresponding active region of the active regions. The memory device includes contact-to-transistor-component structures (MD structures), each of the MD structures is over a second portion of a corresponding active region, and a first MD structure is between adjacent gate structures. The memory device includes via-to-gate/MD (VGD) structures, each of the VGD structures is over to a corresponding gate electrode and MD structure. The memory device includes conductive segments, each of the conductive segments is over and electrically coupled to a corresponding VGD structure. The memory device includes buried contact-to-transistor-component structures (BVD) structures, each of the BVD structures is under a third portion of a corresponding active region.

Abstract: The invention discloses a vessel automatic berthing wireless charging integrated system and operating method thereof. The invention comprises a charging barge and at least one vessel. The charging barge comprises a power, a distribution board and a locking module control system, and every vessel comprises an automatic pilot system, a vessel controlling system and a wireless power receiving module. A bow berthing module of the present invention moors the vessel. After a guiding structure of the bow berthing module straightly aligns bow direction of the vessel, a wireless power supplying module of a side berthing module matches with the wireless power receiving module then charges the vessel.

Abstract: A memory device includes a conductive segment, first and second rows of memory cells. The conductive segment receives a first reference voltage signal. The first row of memory cells is coupled to a first word line. The second row of memory cells is coupled to a second word line. The first row of memory cells includes first and second memory cells. The first memory cell is coupled to the conductive segment to receive the first reference voltage signal. The second row of memory cells includes third and fourth memory cells. The third memory cell is coupled to the conductive segment to receive the first reference voltage signal. The first and third memory cells share the conductive segment, and the third memory cell is arranged between the first and second memory cells. The second memory cell is arranged between the third and fourth memory cells.

Abstract: An operation method of electronic device, comprising providing a first panel, wherein the first panel comprises first substrate, first medium layer disposed on the first substrate, a first electrode layer disposed between the first substrate and the first medium layer, and a second electrode layer disposed between the first electrode layer and the first medium layer; providing a second panel overlapped with the first panel, providing an adhesive layer, wherein the first panel is attached to the second panel through the adhesive layer, and the first panel and the second panel present a mirror-symmetrical structure with the adhesive layer as the axis of symmetry; applying a first voltage to the first electrode layer; applying a second voltage to the second electrode layer; applying a third voltage to the first electrode layer.

Abstract: A semiconductor device includes a dummy fin structure disposed over a substrate, a dummy gate structure disposed over a part of the dummy fin structure, a first interlayer dielectric layer in which the dummy gate structure is embedded, a second interlayer dielectric layer disposed over the first interlayer dielectric layer, and a resistor wire formed of a conductive material and embedded in the second interlayer dielectric layer. The resistor wire overlaps the dummy gate structure in plan view.

Abstract: An electrically tunable liquid crystal lens includes a carrier substrate, a common electrode layer disposed on the carrier substrate, a liquid crystal unit, a patterned electrode layer, a terminal electrode layer, a dielectric insulating layer, and a cover. The liquid crystal unit is disposed on the common electrode layer opposite to the carrier substrate, and includes a plurality of liquid crystal molecules. The patterned electrode layer is disposed on the liquid crystal unit opposite to the common electrode layer, and has a plurality of aperture patterns located within a projection of the liquid crystal unit on the patterned electrode layer. The terminal electrode layer is disposed on the patterned electrode layer opposite to the liquid crystal unit. The dielectric insulating layer is disposed between the patterned electrode layer and the terminal electrode layer. The cover is disposed on the terminal electrode layer opposite to the dielectric insulating layer.

Abstract: A method for forming a semiconductor device includes receiving a substrate having a first opening and a second opening formed thereon, wherein the first opening has a first width, and the second opening has a second width less than the first width; forming a protecting layer to cover the first opening and expose the second opening; performing a wet etching to widen the second opening with an etchant, wherein the second opening has a third width after the performing of the wet etching, and the third width of the second opening is substantially equal to the first width of the first opening; and performing a photolithography to transfer the first opening and the second opening to a target layer.

Abstract: A bonding apparatus includes a vacuum holder and a thermal head. The vacuum holder is configured to attach a non-bonding area of a printed circuit board. A side of the vacuum holder has a first lower sidewall, a first upper sidewall, and a first connection surface adjoining the first lower sidewall and the first upper sidewall. The thermal head is adjacent to the vacuum holder and configured to hot press a bonding area of the printed circuit board. A side of the thermal head proximal to the vacuum holder has a second lower sidewall, a second upper sidewall, and a second connection surface adjoining the second lower sidewall and the second upper sidewall. The second connection surface overlaps at least a portion of the first connection surface, and a height of the second lower sidewall is greater than a height of the first lower sidewall.

Abstract: The present invention relates to cabozantinib lauryl sulfate salt and methods of use.

Abstract: The present invention relates to capsules comprising dasatinib lauryl sulfate salt.