Patents by Inventor Yi-Hsin Liu

Yi-Hsin Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12164235
    Abstract: Some implementations described herein include operating components in a lithography system at variable speeds to reduce, minimize, and/or prevent particle generation due to rubbing of or collision between contact parts of the components. In some implementations, a component in a path of transfer of a semiconductor substrate in the lithography system is operated at a relatively high movement speed through a first portion of an actuation operation, and is operated at a reduced movement speed (e.g., a movement speed that is less than the high movement speed) through a second portion of the actuation operation in which contact parts of the component are to interact. The reduced movement speed reduces the likelihood of particle generation and/or release from the contact parts when the contact parts interact, while the high movement speed provides a high semiconductor substrate throughput in the lithography system.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: December 10, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shao-Hua Wang, Kueilin Ho, Cheng Wei Sun, Zong-You Yang, Chih-Chun Chiang, Yi-Fam Shiu, Chueh-Chi Kuo, Heng-Hsin Liu, Li-Jui Chen
  • Publication number: 20240379789
    Abstract: A method to form a transistor device with a recessed gate structure is provided. In one embodiment, a gate structure is formed overlying a device region and an isolation structure. The gate structure separates a device doping well along a first direction with a pair of recess regions disposed on opposite sides of the device region in a second direction perpendicular to the first direction. A pair of source/drain regions in is formed the device region on opposite sides of the gate structure. A sidewall spacer is formed extending along sidewalls of the gate structure, where a top surface of the sidewall spacer is substantially flush with the top surface of the gate structure. A resistive protection layer is then formed on the sidewall spacer and covering the pair of recess regions.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Inventors: Chen-Liang Chu, Chien-Chih Chou, Chih-Chang Cheng, Yi-Huan Chen, Kong-Beng Thei, Ming-Ta Lei, Ruey-Hsin Liu, Ta-Yuan Kung
  • Publication number: 20240366603
    Abstract: The present invention relates methods for treating chronic myeloid leukemia and/or lymphoblastic leukemia by orally administering to a patient in need of such a therapeutic amount of dasatinib lauryl sulfate salt, preferably in a tablet, capsule or suspension form. The method allows the administration of the therapeutic amount of dasatinib lauryl sulfate salt a fed state or a fasted state and the administration does not exhibit a food effect.
    Type: Application
    Filed: July 19, 2024
    Publication date: November 7, 2024
    Applicant: Handa Oncology, LLC
    Inventors: Fang-Yu Liu, K.C. Sung, Chin-Yao Yang, Chi-Cheng Lin, Yi-Hsin Lin, Li Qiao
  • Patent number: 12106033
    Abstract: The present disclosure describes a method for optimizing metal cuts in standard cells. The method includes placing a standard cell in a layout area and inserting a metal cut along a metal interconnect of the standard cell at a location away from a boundary of the standard cell. The method further includes disconnecting, at the location, a metal portion of the metal interconnect from a remaining portion of the metal interconnect based on the metal cut.
    Type: Grant
    Filed: June 26, 2023
    Date of Patent: October 1, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheok-Kei Lei, Zhe-Wei Jiang, Chi-Yu Lu, Yi-Hsin Ko, Chi-Lin Liu, Hui-Zhong Zhuang
  • Publication number: 20240304741
    Abstract: A cell module is provided. The cell module includes a first substrate; a second substrate disposed opposite to the first substrate; a cell unit disposed between the first substrate and the second substrate; a first thermosetting resin layer disposed between the cell unit and the first substrate; a first protective layer disposed between the cell unit and the first thermosetting resin layer; and a second thermosetting resin layer disposed between the cell unit and the second substrate. The first protective layer includes a first polymer, wherein the cross-linking degree of the first polymer is 0 to 42.3%.
    Type: Application
    Filed: November 30, 2023
    Publication date: September 12, 2024
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chiou-Chu LAI, Chun-Wei SU, Yi-Chun LIU, Hsin-Hsin HSIEH, Hsin-Chung WU, En-Yu PAN, Chin-Ping HUANG
  • Patent number: 12064428
    Abstract: The present invention relates to capsules comprising dasatinib lauryl sulfate salt.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: August 20, 2024
    Assignee: HANDA ONCOLOGY, LLC
    Inventors: Fang-Yu Liu, K. C. Sung, Chin-Yao Yang, Chi-Cheng Lin, Yi-Hsin Lin, Li Qiao
  • Patent number: 12064430
    Abstract: The present invention relates to cabozantinib lauryl sulfate salt and methods of use.
    Type: Grant
    Filed: January 13, 2023
    Date of Patent: August 20, 2024
    Assignee: Handa Oncology, LLC
    Inventors: Fang-Yu Liu, K. C. Sung, Chin-Yao Yang, Chi-Cheng Lin, Yi-Hsin Lin, Li Qiao
  • Publication number: 20240264405
    Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a stopping assembly. The fixed assembly has a main axis. The movable assembly is configured to connect an optical element, and the movable assembly is movable relative to the fixed assembly. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The stopping assembly is configured to limit the movement of the movable assembly relative to the fixed assembly within a range of motion.
    Type: Application
    Filed: April 16, 2024
    Publication date: August 8, 2024
    Inventors: Chao-Chang HU, Liang-Ting HO, Chen-Er HSU, Yi-Liang CHAN, Fu-Lai TSENG, Fu-Yuan WU, Chen-Chi KUO, Ying-Jen WANG, Wei-Han HSIA, Yi-Hsin TSENG, Wen-Chang LIN, Chun-Chia LIAO, Shou-Jen LIU, Chao-Chun CHANG, Yi-Chieh LIN, Shang-Yu HSU, Yu-Huai LIAO, Shih-Wei HUNG, Sin-Hong LIN, Kun-Shih LIN, Yu-Cheng LIN, Wen-Yen HUANG, Wei-Jhe SHEN, Chih-Shiang WU, Sin-Jhong SONG, Che-Hsiang CHIU, Sheng-Chang LIN
  • Patent number: 12046680
    Abstract: A semiconductor structure comprises a plurality of gate structures alternately stacked with a plurality of channel layers, and a plurality of spacers disposed on lateral sides of the plurality of gate structures. The respective ones of the plurality of spacers comprise a profile having a first portion comprising a first shape and a second portion comprising a second shape, wherein the first shape is different from the second shape.
    Type: Grant
    Filed: September 27, 2021
    Date of Patent: July 23, 2024
    Assignee: International Business Machines Corporation
    Inventors: Yi Song, Chi-Chun Liu, Robin Hsin Kuo Chao, Muthumanickam Sankarapandian
  • Publication number: 20240128214
    Abstract: An integrated circuit structure includes an aluminum pad layer on a dielectric stack, a passivation layer covering the aluminum pad layer, and an aluminum shield layer including aluminum routing patterns disposed directly above an embedded memory area and embedded in the dielectric stack. The aluminum shield layer is electrically connected to the uppermost copper layer through a plurality of tungsten vias. The plurality of tungsten vias is embedded in the dielectric stack.
    Type: Application
    Filed: December 28, 2023
    Publication date: April 18, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Aaron Chen, Chi Ren, Yi Hsin Liu
  • Patent number: 11901318
    Abstract: An integrated circuit structure includes a substrate with a circuit region thereon and a copper interconnect structure disposed on the substrate. The copper interconnect structure includes an uppermost copper layer covered by a dielectric layer. An aluminum pad layer is provided on the dielectric layer. A metal layer is provided on the circuit region and is located between the uppermost copper layer and the aluminum pad layer.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: February 13, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Aaron Chen, Chi Ren, Yi Hsin Liu
  • Publication number: 20230168214
    Abstract: A preparation method of monolayer two-dimensional materials, including the following steps: providing a metal acetate dihydrate, with a general formula M(CH3COO)2.2H2O, in which M may be metal ion cadmium or zinc. Dissolving the metal acetate dihydrate in ethylene diamine and heating to 60° C. for two hours to form a metal cation precursor solution. Providing a chalcogen element powder, in which the chalcogen element powder is selected from sulfur, selenium, or tellurium. Dissolving the chalcogen element powder and sodium borohydride in ethylene diamine, and standing at room temperature for 24 hours to form a chalcogenide-amine precursor solution. Mixing the metal cation precursor solution with the chalcogenide-amine precursor solution to form a mixed solution. Transferring the mixed solution in a high temperature autoclave for reaction to form the monolayer two-dimensional materials.
    Type: Application
    Filed: February 11, 2022
    Publication date: June 1, 2023
    Inventors: YI-HSIN LIU, KAI-CHUN CHUANG, CHI LI, SHENG-CHIH HSU
  • Publication number: 20220262749
    Abstract: An integrated circuit structure includes a substrate with a circuit region thereon and a copper interconnect structure disposed on the substrate. The copper interconnect structure includes an uppermost copper layer covered by a dielectric layer. An aluminum pad layer is provided on the dielectric layer. A metal layer is provided on the circuit region and is located between the uppermost copper layer and the aluminum pad layer.
    Type: Application
    Filed: January 28, 2021
    Publication date: August 18, 2022
    Inventors: Aaron Chen, CHI REN, YI HSIN LIU
  • Publication number: 20160282274
    Abstract: The present invention disclosed a mesoporous silica thin film with perpendicular nanochannels on a substrate, a process of forming the same and the application in surface-enhanced Raman spectroscopy. Furthermore, a gold nanoparticle array on a mesoporous silica material with perpendicular nanochannels and the process of forming the same is also present in the invention.
    Type: Application
    Filed: March 3, 2016
    Publication date: September 29, 2016
    Inventors: Chung-Yuan Mou, Kun-Che Kao, Tzu-Ying Chen, Yi-Wen Wang, Yi-Hsin Liu
  • Patent number: 9115724
    Abstract: A blade structure and ceiling fan having the same are disclosed. The blade structure includes a blade root, a blade tip, and a first vertex and a second vertex between the blade root and the blade tip. The blade bends from blade root to the first vertex, the blade tip and then bends from the blade tip to the second vertex and back to the blade root to form a hollow structure. The ceiling fan with the blade structure not only provides air modulating function but also has unique modeling.
    Type: Grant
    Filed: October 17, 2012
    Date of Patent: August 25, 2015
    Assignee: PAN AIR ELECTRIC CO., LTD.
    Inventors: Chui-Yuan Chen, Yi-Hsin Liu
  • Patent number: 9025830
    Abstract: A liveness detection method comprising: receiving plural pictures of a video stream comprising a face and an adjacent background; determining motion of the face and the background, the motion determined over the plural pictures; comparing the motion between the face and the background; and determining whether the face corresponds to an actual, live user or an image of the user based on the comparison, the determinations performed by a processor.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: May 5, 2015
    Assignee: Cyberlink Corp.
    Inventors: Chih-Chao Ma, Yi-Hsin Liu
  • Publication number: 20140270412
    Abstract: A liveness detection method comprising: receiving plural pictures of a video stream comprising a face and an adjacent background; determining motion of the face and the background, the motion determined over the plural pictures; comparing the motion between the face and the background; and determining whether the face corresponds to an actual, live user or an image of the user based on the comparison, the determinations performed by a processor.
    Type: Application
    Filed: May 29, 2014
    Publication date: September 18, 2014
    Applicant: Cyberlink Corp.
    Inventors: Chih-Chao Ma, Yi-Hsin Liu
  • Publication number: 20130188840
    Abstract: A liveness detection method comprising: receiving plural pictures of a video stream comprising a face and an adjacent background; determining motion of the face and the background, the motion determined over the plural pictures; comparing the motion between the face and the background; and determining whether the face corresponds to an actual, live user or an image of the user based on the comparison, the determinations performed by a processor.
    Type: Application
    Filed: January 20, 2012
    Publication date: July 25, 2013
    Applicant: CYBERLINK CORP.
    Inventors: Chih-Chao Ma, Yi-Hsin Liu