Patents by Inventor Yi-Hsin (Simon) Liu
Yi-Hsin (Simon) Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250220868Abstract: An integrated circuit chip includes a first and a second memory cell array, and a first and a second set of bit lines. The first memory cell array has a first width in a first direction, and a first height in a second direction. The second memory cell array has a second width in the first direction and a second height in the second direction. The first set of bit lines extends in the first direction, is coupled to the first memory cell array, overlaps the first memory cell array, and is on a first metal layer. The second set of bit lines extends in the first direction, is coupled to the second memory cell array, overlaps the second memory cell array, and is on the first metal layer. At least the first width is different from the second width, or the first height is different from the second height.Type: ApplicationFiled: June 18, 2024Publication date: July 3, 2025Inventors: Yi-Hsin NIEN, Chih-Yu LIN, Hidehiro FUJIWARA, Yen-Huei CHEN
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Publication number: 20250207263Abstract: A surface-modified aluminum alloy substrate structure includes a 6000-Series aluminum alloy substrate, a diffusion buffer layer, and a meltable metallic layer. The diffusion buffer layer is formed on the 6000-Series aluminum alloy substrate for buffering magnesium in the 6000-Series aluminum alloy substrate from diffusing to a meltable metallic layer. The meltable metallic layer is formed on the diffusion buffer layer for being melted in a subsequent process.Type: ApplicationFiled: December 26, 2023Publication date: June 26, 2025Inventors: YI-HSIN HUANG, CHING-MING YANG, KUO-WEI LEE, TZE-YANG YEH
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Publication number: 20250207868Abstract: A liquid cooler having an aluminum brazing bead structure includes a first outer cover, a second outer cover, a plurality of water holes formed on at least one of the first outer cover and the second outer cover, a liquid flow channel formed between the first outer cover and the second outer cover and in spatial communication with the water holes, at least one divider island integrally formed on the second outer cover and dividing the liquid flow channel into a plurality of sub-flow channels, and one or more open holes formed between the at least one divider island and the first outer cover. An upper surface of the at least one divider island and a lower surface of the first outer cover are brazed together, so that the one or more open holes are formed into one or more blind holes.Type: ApplicationFiled: December 21, 2023Publication date: June 26, 2025Inventors: CHING-MING YANG, REUI-JEN YANG, YI-HSIN HUANG, KUO-WEI LEE, TZE-YANG YEH
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Patent number: 12326573Abstract: An optical system includes a pancake lens assembly which has a lens unit and a liquid crystal device. The lens unit includes a partially reflective mirror, a reflective polarizer, and a quarter waveplate disposed between the partially reflective mirror and the reflective polarizer. The liquid crystal device is disposed between the quarter waveplate and the reflective polarizer. When a light is introduced into the pancake lens assembly in a Z direction, an X-polarized light passes through the liquid crystal device two times and a Y-polarized light passes through the liquid crystal device one time.Type: GrantFiled: February 9, 2022Date of Patent: June 10, 2025Assignee: NATIONAL YANG MING CHIAO TUNG UNIVERSITYInventors: Yu-Jen Wang, Yi-Hsin Lin
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Patent number: 12299373Abstract: A method of designing a semiconductor device including the operations of analyzing a vertical abutment between a first standard cell block and a second cell block and, if a mismatch is identified between the first standard cell block and the second cell block initiating the selection of a first modified cell block that reduces the mismatch and a spacing between the first modified cell block and the second cell block, the first modified cell block comprising a first abutment region having a continuous active region arranged along a first axis parallel to an edge of the vertical abutment, and replacing the first standard cell block with the first modified cell block to obtain a first modified layout design and devices manufactured according to the method.Type: GrantFiled: August 9, 2023Date of Patent: May 13, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chi-Yu Lu, Hui-Zhong Zhuang, Pin-Dai Sue, Yi-Hsin Ko, Li-Chun Tien
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Publication number: 20250142920Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The method includes forming a metal gate stack wrapped around multiple semiconductor nanostructures, and the semiconductor nanostructures are adjacent to an epitaxial structure. The method also includes forming a dielectric layer over the metal gate stack and the epitaxial structure and partially removing the dielectric layer to form a contact opening exposing the epitaxial structure. The method further includes forming a first protective layer over sidewalls of the contact opening and forming a second protective layer over the first protective layer. The first protective layer has a lower dielectric constant than that of the second protective layer. In addition, the method includes forming a conductive contact over the second protective layer and the epitaxial structure to fill the contact opening.Type: ApplicationFiled: October 25, 2023Publication date: May 1, 2025Inventors: Yi-Ren CHEN, Che-Chia CHANG, Po-Cheng CHI, Yi-Hsin TING
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Publication number: 20250142756Abstract: Methods, systems, and devices for providing computer implemented services are disclosed. To provide the computer implemented services, a data processing system may include various hardware components. To secure the various hardware components, the data processing system may include a security bezel. The security bezel may for a chassis of the data processing system, the hardware components being positioned on an interior of the chassis. The security bezel may have a structural body that has a length that is equal to or less than a length of a two-dimensional surface through which access to the interior is provided. The security bezel may further have an adjustable member adapted to adjust a length of the structural bezel to match the length of the surface while reversibly securing the structural body to the chassis.Type: ApplicationFiled: October 27, 2023Publication date: May 1, 2025Inventors: SEAN P. O’DONNELL, YI-HSIN KUAN, MATTHEW BRYAN GILBERT, NICHOLAS LENN POTERACKI, KEVIN MICHAEL KELLER
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Publication number: 20250142758Abstract: Methods, systems, and devices for providing computer implemented services are disclosed. To provide the computer implemented services, a data processing system may include various hardware components. To secure the various hardware components, the data processing system may include a security bezel. The security bezel may for a chassis of the data processing system, the hardware components being positioned on an interior of the chassis. The security bezel may have a hollow cover body spanning a two-dimensional surface through which access to the interior is provided. The security bezel may further have a latch mechanism adapted to reversibly secure the hollow cover body to the chassis.Type: ApplicationFiled: October 27, 2023Publication date: May 1, 2025Inventors: YI-HSIN KUAN, PETER TIMOTHY CLARK, PATRICK VINCENT ILLINGWORTH, JAMES UTZ, MARIO ALBERTO ROCHA RINCON
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Publication number: 20250138676Abstract: An electronic device including a display panel and a CPU is provided. The display panel updates displayed images at a refresh rate. The CPU implements a latency monitor, a system resource controller, a display controller, and an application. The latency monitor collects time information related to touch latency. The touch latency is the duration between the time point at which the display panel detects a touch event and the time point at which the display panel displays an image generated by the application in response to said touch event. The display controller informs the system resource controller of the refresh rate. The system resource controller adjusts the resource allocation of the electronic device to cause the touch latency to be lower than a threshold, according to the time information and the refresh rate.Type: ApplicationFiled: October 25, 2024Publication date: May 1, 2025Inventors: Yi-Hsin SHEN, Nien-Hsien LIN, Yen-Po CHIEN, Yen-An SHIH, Chiu-Jen LIN, Cheng-Che CHEN
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Publication number: 20250132355Abstract: A flow battery stack is provided with carbon-felt electrodes etched with canals. The stack comprises carbon-felt electrodes, bipolar plates, separating membranes, and electrolytes. A plurality of canals are etched on the surface of the electrode to increase the flow rate of electrolyte for improving reactivity. With the carbon-felt electrodes used in the flow battery stack, a long-term and stable charging/discharging operation is achieved with the cost of electricity storage effectively reduced.Type: ApplicationFiled: April 1, 2024Publication date: April 24, 2025Inventors: Chien-Hong Lin, Yi-Hsin Hu, Ning-Yih Hsu, Hwa-Jou Wei
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Patent number: 12283557Abstract: An integrated circuit structure includes an aluminum pad layer on a dielectric stack, a passivation layer covering the aluminum pad layer, and an aluminum shield layer including aluminum routing patterns disposed directly above an embedded memory area and embedded in the dielectric stack. The aluminum shield layer is electrically connected to the uppermost copper layer through a plurality of tungsten vias. The plurality of tungsten vias is embedded in the dielectric stack.Type: GrantFiled: December 28, 2023Date of Patent: April 22, 2025Assignee: UNITED MICROELECTRONICS CORP.Inventors: Aaron Chen, Chi Ren, Yi Hsin Liu
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Publication number: 20250124966Abstract: A memory device includes a memory array including a plurality of word lines, each of the plurality of word lines operatively coupled to a corresponding set of memory cells, and a controller operatively coupled to the memory array. The controller is configured to receive a first address signal indicating a first word line that is physically arranged with respect to the controller by a first distance, assert the first word line through a first signal with a first pulse width, receive a second address signal indicating a second word line that is physically arranged with respect to the controller by a second distance, assert the second word line through a second signal with a second pulse width, and adjust one of the first pulse width or the second pulse width based on the first distance and the second distance.Type: ApplicationFiled: January 2, 2024Publication date: April 17, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hidehiro Fujiwara, Yi-Hsin Nien, Venkateswara Reddy Konudula, Nikhil Puri, Yen-Huei Chen
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Publication number: 20250118632Abstract: A memory device may comprise a substrate, a plurality of memory cells, and a header device. The substrate may have a first side and a second side opposite to each other. The plurality of memory cells may be formed on the first side of the substrate. The header device may be formed on the first side of the substrate. The header device can be configured to selectively couple a supply voltage through a first combination of power delivery paths or a second combination of power delivery paths to the plurality of memory cells based on a control signal.Type: ApplicationFiled: October 10, 2023Publication date: April 10, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Hsin Nien, Chih-Yu Lin, Hidehiro Fujiwara, Yen-Huei Chen
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Publication number: 20250112052Abstract: Disclosed herein are methods for forming opening ends within semiconductor structures. In some embodiments, a method may include providing an opening formed in a layer of a semiconductor device, wherein the opening comprises a set of sidewalls opposite one another, and first and second end walls connected to the sidewalls, wherein each of the first and second end walls defines a tip end and a set of curved sections extending between the tip end and the set of sidewall. The method may further include performing an ion etch to the opening by delivering an ion beam at a non-zero angle relative to a plane defined by the layer of the semiconductor device, wherein the ion etch comprises a lean-gas chemistry, and wherein the ion etch causes the layer of the semiconductor device to be removed faster along the set of curved sections than along the set of sidewalls.Type: ApplicationFiled: September 29, 2023Publication date: April 3, 2025Applicant: Applied Materials, Inc.Inventors: Yi-Hsin CHEN, Kevin R. Anglin, Yong Yang, Solomon Belangedi Basame, Yung-Chen Lin, Gang Shu
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Publication number: 20250112984Abstract: A mobile electronic device and a call volume adjustment method thereof are provided. The call volume adjustment method is adapted to the mobile electronic device and includes the following steps. A callee of a call is identified. Whether a call record list includes the callee is judged. A call volume of the call is adjusted according to the callee based on record data in the call record list when the call record list includes the callee.Type: ApplicationFiled: August 9, 2024Publication date: April 3, 2025Applicant: ASUSTeK COMPUTER INC.Inventors: Yi-Hsin Shang, Jen-Pang Hsu, Chao-Hsien Huang
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Patent number: 12266412Abstract: A content addressable memory (CAM) and a CAM cell are provided. The CAM includes a memory cell array and a disabling circuit. The memory cell array includes a plurality of CAM cells, wherein each of the CAM cells includes a memory cell circuit and a comparison circuit. When the CAM cells in a first column of the memory cell array are normal, the disabling circuit enables the comparison circuits of the CAM cells in the first column, so that the comparison circuits in the first column respectively present the comparison results on different match lines. When any one of the CAM cells in the first column is defective, the disabling circuit disables the comparison circuits of the CAM cells in the first column, so that the disabled comparison circuits does not affect the different match lines.Type: GrantFiled: May 25, 2023Date of Patent: April 1, 2025Assignee: Faraday Technology Corp.Inventors: Yi-Hsin Tseng, Chi-Chang Shuai, Yen-Yao Wang
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Patent number: 12260903Abstract: A memory array is disclosed. The memory array includes a plurality of memory cells disposed over a substrate. Each of the memory cells is coupled to a corresponding one of a plurality of word lines and a corresponding one of a plurality of bit line pairs. First four of the memory cells that are coupled to four consecutive ones of the word lines and to a first one of the bit line pairs are abutted to one another on the substrate along a single lateral direction.Type: GrantFiled: July 12, 2022Date of Patent: March 25, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Hsin Nien, Hidehiro Fujiwara, Chih-Yu Lin, Yen-Huei Chen
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Publication number: 20250093960Abstract: The embodiments of the disclosure provide a method for controlling a view angle, a host, and a computer readable storage medium. The method includes: providing a visual content, wherein the visual content has a field of view (FOV) corresponding to a first view angle; in response to determining that a preparation gesture is detected, displaying a visual cue in the visual content, wherein the visual cue indicates a first direction; and in response to determining that the preparation gesture has been changed to a first gesture corresponding to the first direction, adjusting the FOV to correspond to a second view angle based on the first direction.Type: ApplicationFiled: March 6, 2024Publication date: March 20, 2025Applicant: HTC CorporationInventor: Yi-Hsin Chang
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Publication number: 20250078889Abstract: Systems and method are provided for a memory circuit. In embodiments, the circuit includes a plurality of memory cells corresponding to a word of data and a global write word line. A plurality of local write lines are connected to a subset of the plurality of memory cells of the word of data. Selection logic is configured to activate a particular subset of memory cells for writing via a particular local write line based on a signal on the global write word line and a selection signal associated with the particular subset of memory cells.Type: ApplicationFiled: November 15, 2024Publication date: March 6, 2025Inventors: Yi-Hsin Nien, Hidehiro Fujiwara, Yen-Huei Chen
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Patent number: 12234396Abstract: An optical adhesive film structure having an alignment function is provided. The optical adhesive film structure includes an optical adhesive layer and a release film. The release film is disposed on the optical adhesive layer. A first film surface of the release film facing away from the optical adhesive layer has a plurality of marks. The marks are recessed into the release film relative to the first film surface and do not run through the release film. A stitching display module and a manufacturing method of the stitching display module are also provided.Type: GrantFiled: December 8, 2022Date of Patent: February 25, 2025Assignee: AUO CORPORATIONInventors: Yi-Hsin Lin, Wen-Lung Chen, Yu-Chin Wu, Wei-Lung Liau