Patents by Inventor Yi-Hsiu Hsiao

Yi-Hsiu Hsiao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220149041
    Abstract: A semiconductor device includes a substrate, a gate stack, and epitaxy structures. The substrate has a P-type region. The gate stack is over the P-type region of the substrate and includes a gate dielectric layer, a bottom work function (WF) metal layer, a top WF metal layer, and a filling metal. The bottom WF metal layer is over the gate dielectric layer. The top WF metal layer is over and in contact with the bottom WF metal layer. Dipoles are formed between the top WF metal layer and the bottom WF metal layer, and the dipoles direct from the bottom WF metal layer to the top WF metal layer. The filling metal is over the top WF metal layer. The epitaxy structures are over the P-type region of the substrate and on opposite sides of the gate stack.
    Type: Application
    Filed: January 26, 2022
    Publication date: May 12, 2022
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Chih-Hsiung HUANG, Chung-En TSAI, Chee-Wee LIU, Kun-Wa KUOK, Yi-Hsiu HSIAO
  • Patent number: 11244945
    Abstract: A semiconductor device includes a substrate, a gate stack, and an epitaxy structure. The gate stack over the substrate and includes a gate dielectric layer, a bottom work function (WF) metal layer, a top WF metal layer, and a filling metal. The bottom WF metal layer is over the gate dielectric layer. The top WF metal layer is over and in contact with the bottom WF metal layer. At least one of the top and bottom WF metal layers includes dopants, and the top WF metal layer is thicker than the bottom WF metal layer. The filling metal is over the top WF metal layer. The epitaxy structure is over the substrate and adjacent the gate stack.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: February 8, 2022
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Chih-Hsiung Huang, Chung-En Tsai, Chee-Wee Liu, Kun-Wa Kuok, Yi-Hsiu Hsiao
  • Publication number: 20210057408
    Abstract: A semiconductor device includes a substrate, a gate stack, and an epitaxy structure. The gate stack over the substrate and includes a gate dielectric layer, a bottom work function (WF) metal layer, a top WF metal layer, and a filling metal. The bottom WF metal layer is over the gate dielectric layer. The top WF metal layer is over and in contact with the bottom WF metal layer. At least one of the top and bottom WF metal layers includes dopants, and the top WF metal layer is thicker than the bottom WF metal layer. The filling metal is over the top WF metal layer. The epitaxy structure is over the substrate and adjacent the gate stack.
    Type: Application
    Filed: August 22, 2019
    Publication date: February 25, 2021
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Chih-Hsiung HUANG, Chung-En TSAI, Chee-Wee LIU, Kun-Wa KUOK, Yi-Hsiu HSIAO
  • Publication number: 20100127428
    Abstract: A composite bipolar plate for a polymer electrolyte membrane membrane fuel cell (PEMFC) is prepared as follows: a) melt compounding a polypropylene resin and graphite powder at 100-250° C. and 30-150 rpm to form a melt compounding material, the graphite powder content ranging from 50 wt % to 95 wt % based on the total weight of the graphite powder and the polypropylene resin, and the polypropylene resin being a homopolymer of propylene or a copolymer of propylene and ethylene, wherein 0.05-20 wt % carbon nanotubes, based on the weight of the polypropylene resin, are added during the melt compounding; and b) molding the melt compounding material from step a) to form a bipolar plate having a desired shaped at 100-250° C. and 500-4000 psi.
    Type: Application
    Filed: July 20, 2009
    Publication date: May 27, 2010
    Applicant: YUAN ZE UNIVERSITY
    Inventors: Chen-Chi M. Ma, Shu-Hang Liao, Chuan-Yu Yen, Cheng-Chih Weng, Ching-Hung Yang, Ming-Yu Yen, Min-Chien Hsiao, Shuo-Jen Lee, Yi-Hsiu Hsiao