Patents by Inventor Yi-Hsiu Tseng

Yi-Hsiu Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200335431
    Abstract: A semiconductor device package includes a copper lead frame, a copper oxide compound layer and an encapsulant. The copper oxide compound layer is in contact with a surface of the copper lead frame. The copper oxide compound layer includes a copper(II) oxide, and a thickness of the copper oxide compound layer is in a range from about 50 nanometers to about 100 nanometers. The encapsulant is in contact with a surface of the copper oxide compound layer.
    Type: Application
    Filed: July 6, 2020
    Publication date: October 22, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Min-Fong SHU, Yi-Hsiu TSENG
  • Patent number: 9984993
    Abstract: A method of manufacturing a bonding structure includes (a) providing a substrate, wherein the substrate includes a top surface and at least one bonding pad disposed adjacent to the top surface of the substrate, at least one bonding pad having a sloped surface with a first slope; (b) providing a semiconductor element, wherein the semiconductor element includes at least one pillar, and at least one pillar has a sidewall with a second slope, wherein the absolute value of the first slope is smaller than the absolute value of the second slope; and (c) bonding at least one pillar to a portion of the sloped surface of corresponding ones of the at least one bonding pad.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: May 29, 2018
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Min-Fong Shu, Yi-Hsiu Tseng, Kuan-Neng Chen, Shu-Chiao Kuo
  • Publication number: 20180076118
    Abstract: A semiconductor device package includes a copper lead frame, a copper oxide compound layer and an encapsulant. The copper oxide compound layer is in contact with a surface of the copper lead frame. The copper oxide compound layer includes a copper(II) oxide, and a thickness of the copper oxide compound layer is in a range from about 50 nanometers to about 100 nanometers. The encapsulant is in contact with a surface of the copper oxide compound layer.
    Type: Application
    Filed: August 25, 2017
    Publication date: March 15, 2018
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Min-Fong SHU, Yi-Hsiu TSENG
  • Publication number: 20170033075
    Abstract: A method of manufacturing a bonding structure includes (a) providing a substrate, wherein the substrate includes a top surface and at least one bonding pad disposed adjacent to the top surface of the substrate, at least one bonding pad having a sloped surface with a first slope; (b) providing a semiconductor element, wherein the semiconductor element includes at least one pillar, and at least one pillar has a sidewall with a second slope, wherein the absolute value of the first slope is smaller than the absolute value of the second slope; and (c) bonding at least one pillar to a portion of the sloped surface of corresponding ones of the at least one bonding pad.
    Type: Application
    Filed: October 14, 2016
    Publication date: February 2, 2017
    Inventors: Min-Fong SHU, Yi-Hsiu TSENG, Kuan-Neng CHEN, Shu-Chiao KUO
  • Patent number: 9496238
    Abstract: A bonding structure includes a substrate having a top surface and including at least one bonding pad. Each bonding pad is disposed adjacent to the top surface of the substrate and has a sloped surface. A semiconductor element includes at least one pillar. Each pillar is bonded to a portion of the sloped surface of a corresponding bonding pad, and a gap is formed between a sidewall of the pillar and the sloped surface of the corresponding bonding pad.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: November 15, 2016
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Min-Fong Shu, Yi-Hsiu Tseng, Kuan-Neng Chen, Shu-Chiao Kuo
  • Publication number: 20160240503
    Abstract: The present disclosure relates to bonding structures useful in semiconductor packages and methods of manufacturing the same. In an embodiment, the bonding structure comprises a substrate, having a top surface and including at least one bonding pad, wherein each bonding pad is disposed adjacent to the top surface of the substrate and has a sloped surface; and a semiconductor element including at least one pillar, wherein each pillar is bonded to a portion of the sloped surface of a corresponding bonding pad, and a gap is formed between a sidewall of the pillar and the sloped surface of the corresponding bonding pad.
    Type: Application
    Filed: February 13, 2015
    Publication date: August 18, 2016
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Min-Fong Shu, Yi-Hsiu TSENG, Kuan-Neng CHEN, Shu-Chiao KUO
  • Patent number: 8375200
    Abstract: A file change notification method of an embedded device that includes a first operating system (OS) and a second OS. The first OS corresponds to a first central processing unit (CPU) and connects to a storage system, the second OS corresponds to a second CPU for sharing with the configuration file via a network file system (NFS). The method monitors the configuration file stored in the storage system, determines whether the configuration file has been modified, and generates a notification message to notify a first application program that the configuration file has been changed. The method further sends the notification message from the first OS to the second OS through a communication network, and notifies a second application program that the configuration file has been changed when the notification message is received from the first OS.
    Type: Grant
    Filed: November 24, 2010
    Date of Patent: February 12, 2013
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventors: Chien-Hua Chen, Yi-Hsiu Tseng
  • Publication number: 20120036345
    Abstract: A file change notification method of an embedded device that includes a first operating system (OS) and a second OS. The first OS corresponds to a first central processing unit (CPU) and connects to a storage system, the second OS corresponds to a second CPU for sharing with the configuration file via a network file system (NFS). The method monitors the configuration file stored in the storage system, determines whether the configuration file has been modified, and generates a notification message to notify a first application program that the configuration file has been changed. The method further sends the notification message from the first OS to the second OS through a communication network, and notifies a second application program that the configuration file has been changed when the notification message is received from the first OS.
    Type: Application
    Filed: November 24, 2010
    Publication date: February 9, 2012
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: CHIEN-HUA CHEN, YI-HSIU TSENG
  • Patent number: 6653235
    Abstract: The present invention provides a fabricating process for forming multi-layered metal bumps by electroless plating, comprising the steps of: providing an IC chip or a semiconductor substrate on which there are provided a plurality of pads; dispensing a first dielectric layer, exposing the pads, roughing the surface to be redistributed by chemical or physical approaches, activating the surface in order to follow-up electroless plating deposition advantageously, and dispensing a second dielectric layer so as to define a redistribution path; depositing a conductive film on the redistribution path by electroless plating, in which the conductive film allows the positions of the pads to be changed so as to be connected to the external circuit; forming a photoresist pattern, exposing a plurality of pre-determined positions on the conductive film so as to redistribute the positions for the metal bumps formed later; performing activation on the pre-determined positions so as to generate an activator; forming initial me
    Type: Grant
    Filed: June 25, 2001
    Date of Patent: November 25, 2003
    Assignee: Industrial Technology Research Institute
    Inventors: Muh-Wang Liang, Yi-Hsiu Tseng, Pang-Min Chiang
  • Publication number: 20020173073
    Abstract: The present invention provides a fabricating process for forming multi-layered metal bumps by electroless plating, comprising the steps of: providing an IC chip or a semiconductor substrate on which there are provided a plurality of pads; dispensing a first dielectric layer, exposing the pads, roughing the surface to be redistributed by chemical or physical approaches, activating the surface in order to follow-up electroless plating deposition advantageously, and dispensing a second dielectric layer so as to define a redistribution path; depositing a conductive film on the redistribution path by electroless plating, in which the conductive film allows the positions of the pads to be changed so as to be connected to the external circuit; forming a photoresist pattern, exposing a plurality of pre-determined positions on the conductive film so as to redistribute the positions for the metal bumps formed later; performing activation on the pre-determined positions so as to generate an activator; forming initial me
    Type: Application
    Filed: June 25, 2001
    Publication date: November 21, 2002
    Applicant: Industrial Technology Research Institute
    Inventors: Muh-Wang Liang, Yi-Hsiu Tseng, Pang-Min Chiang