Patents by Inventor Yi-Hsuan CHUNG
Yi-Hsuan CHUNG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240321731Abstract: A semiconductor device includes a dummy fin structure disposed over a substrate, a dummy gate structure disposed over a part of the dummy fin structure, a first interlayer dielectric layer in which the dummy gate structure is embedded, a second interlayer dielectric layer disposed over the first interlayer dielectric layer, and a resistor wire formed of a conductive material and embedded in the second interlayer dielectric layer. The resistor wire overlaps the dummy gate structure in plan view.Type: ApplicationFiled: June 5, 2024Publication date: September 26, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Hsin HU, Yu-Chiun LIN, Yi-Hsuan CHUNG, Chung-Peng HSIEH, Chung-Chieh YANG, Po-Nien CHEN
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Patent number: 12033937Abstract: A semiconductor device includes a dummy fin structure disposed over a substrate, a dummy gate structure disposed over a part of the dummy fin structure, a first interlayer dielectric layer in which the dummy gate structure is embedded, a second interlayer dielectric layer disposed over the first interlayer dielectric layer, and a resistor wire formed of a conductive material and embedded in the second interlayer dielectric layer. The resistor wire overlaps the dummy gate structure in plan view.Type: GrantFiled: November 16, 2020Date of Patent: July 9, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Hsin Hu, Yu-Chiun Lin, Yi-Hsuan Chung, Chung-Peng Hsieh, Chung-Chieh Yang, Po-Nien Chen
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Publication number: 20240204909Abstract: A data transmission method is provided. The data transmission method may be applied to a first apparatus. The data transmission method may include the following steps. The first apparatus may detect a medium condition to obtain a detection result. Then, the first apparatus may receive channel information from a second apparatus. Then, the first apparatus may obtain punctured sub-channel information corresponding to a transmission bandwidth based on the detection result and the channel information. Then, the first apparatus may transmit a data frame through non-punctured sub-channels of the transmission bandwidth to the second apparatus based on the punctured sub-channel information. Then, the first apparatus may receive an acknowledgement frame from the second apparatus in response to the second apparatus receiving the data frame.Type: ApplicationFiled: December 15, 2023Publication date: June 20, 2024Inventors: Ming-Wang GUO, Tzu-Yun SUNG, Yi-Hsuan CHUNG
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Publication number: 20240188130Abstract: Techniques pertaining to anti-motion and anti-interference frame exchange sequences in wireless communications are described. A station (STA), such as a Wi-Fi equipment, determines to enable a frame exchange sequence (FES). The STA then communicates with one or more other STAs by utilizing the FES in which preamble puncturing sounding and data transmission are performed in a same transmission opportunity (TXOP).Type: ApplicationFiled: October 4, 2023Publication date: June 6, 2024Inventors: Li-Chieh Chen, Kuo-Wei Chen, Chia-Jung Hsu, Yi-Hsuan Chung, Ming-Hsiang Tseng, Wei-Hsu Chen, Cheng-En Hsieh
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Publication number: 20240172273Abstract: Examples pertaining to preamble puncturing negotiation in wireless communications are described. A station (STA) may receive a control frame, and, in response, apply the MRU pattern for one or more transmissions or receptions in a transmission opportunity (TXOP). In the control frame, either a plurality of first reserved bits in a SERVICE field or a plurality of bits in a User Info field are set to indicate a multiple resource unit (MRU) pattern regarding preamble puncturing.Type: ApplicationFiled: November 15, 2023Publication date: May 23, 2024Inventors: Cheng-Yi Chang, Kun-Sheng Huang, Yi-Hsuan Chung, Chung-Kai Hsu, Chia-Hsiang Chang, Kai Ying Lu
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Patent number: 11942375Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming a first semiconductor fin and a second semiconductor fin over a semiconductor substrate. The second semiconductor fin is wider than the first semiconductor fin. The method also includes forming a gate stack over the semiconductor substrate, and the gate stack extends across the first semiconductor fin and the second semiconductor fin. The method further includes forming a first source/drain structure on the first semiconductor fin, and the first source/drain structure is p-type doped. In addition, the method includes forming a second source/drain structure on the second semiconductor fin, and the second source/drain structure is n-type doped.Type: GrantFiled: August 17, 2021Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsing-Hui Hsu, Po-Nien Chen, Yi-Hsuan Chung, Bo-Shiuan Shie, Chih-Yung Lin
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Publication number: 20210375697Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming a first semiconductor fin and a second semiconductor fin over a semiconductor substrate. The second semiconductor fin is wider than the first semiconductor fin. The method also includes forming a gate stack over the semiconductor substrate, and the gate stack extends across the first semiconductor fin and the second semiconductor fin. The method further includes forming a first source/drain structure on the first semiconductor fin, and the first source/drain structure is p-type doped. In addition, the method includes forming a second source/drain structure on the second semiconductor fin, and the second source/drain structure is n-type doped.Type: ApplicationFiled: August 17, 2021Publication date: December 2, 2021Inventors: Hsing-Hui Hsu, Po-Nien Chen, Yi-Hsuan Chung, Bo-Shiuan Shie, Chih-Yung Lin
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Patent number: 11094597Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming a first semiconductor fin and a second semiconductor fin over a semiconductor substrate. The second semiconductor fin is wider than the first semiconductor fin. The method also includes forming a gate stack over the semiconductor substrate, and the gate stack extends across the first semiconductor fin and the second semiconductor fin. The method further includes forming a first source/drain structure on the first semiconductor fin, and the first source/drain structure is p-type doped. In addition, the method includes forming a second source/drain structure on the second semiconductor fin, and the second source/drain structure is n-type doped.Type: GrantFiled: July 30, 2019Date of Patent: August 17, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsing-Hui Hsu, Po-Nien Chen, Yi-Hsuan Chung, Bo-Shiuan Shie, Chih-Yung Lin
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Publication number: 20210066193Abstract: A semiconductor device includes a dummy fin structure disposed over a substrate, a dummy gate structure disposed over a part of the dummy fin structure, a first interlayer dielectric layer in which the dummy gate structure is embedded, a second interlayer dielectric layer disposed over the first interlayer dielectric layer, and a resistor wire formed of a conductive material and embedded in the second interlayer dielectric layer. The resistor wire overlaps the dummy gate structure in plan view.Type: ApplicationFiled: November 16, 2020Publication date: March 4, 2021Inventors: Chia-Hsin HU, Yu-Chiun LIN, Yi-Hsuan CHUNG, Chung-Peng HSIEH, Chung-Chieh YANG, Po-Nien CHEN
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Patent number: 10840181Abstract: A semiconductor device includes a dummy fin structure disposed over a substrate, a dummy gate structure disposed over a part of the dummy fin structure, a first interlayer dielectric layer in which the dummy gate structure is embedded, a second interlayer dielectric layer disposed over the first interlayer dielectric layer, and a resistor wire formed of a conductive material and embedded in the second interlayer dielectric layer. The resistor wire overlaps the dummy gate structure in plan view.Type: GrantFiled: December 21, 2018Date of Patent: November 17, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Hsin Hu, Yu-Chiun Lin, Yi-Hsuan Chung, Chung-Peng Hsieh, Chung-Chieh Yang, Po-Nien Chen
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Publication number: 20200105622Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming a first semiconductor fin and a second semiconductor fin over a semiconductor substrate. The second semiconductor fin is wider than the first semiconductor fin. The method also includes forming a gate stack over the semiconductor substrate, and the gate stack extends across the first semiconductor fin and the second semiconductor fin. The method further includes forming a first source/drain structure on the first semiconductor fin, and the first source/drain structure is p-type doped. In addition, the method includes forming a second source/drain structure on the second semiconductor fin, and the second source/drain structure is n-type doped.Type: ApplicationFiled: July 30, 2019Publication date: April 2, 2020Inventors: Hsing-Hui Hsu, Po-Nien Chen, Yi-Hsuan Chung, Bo-Shiuan Shie, Chih-Yung Lin
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Publication number: 20190148293Abstract: A semiconductor device includes a dummy fin structure disposed over a substrate, a dummy gate structure disposed over a part of the dummy fin structure, a first interlayer dielectric layer in which the dummy gate structure is embedded, a second interlayer dielectric layer disposed over the first interlayer dielectric layer, and a resistor wire formed of a conductive material and embedded in the second interlayer dielectric layer. The resistor wire overlaps the dummy gate structure in plan view.Type: ApplicationFiled: December 21, 2018Publication date: May 16, 2019Inventors: Chia-Hsin HU, Yu-Chiun LIN, Yi-Hsuan CHUNG, Chung-Peng HSIEH, Chung-Chieh YANG, Po-Nien CHEN
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Patent number: 10170414Abstract: A semiconductor device includes a dummy fin structure disposed over a substrate, a dummy gate structure disposed over a part of the dummy fin structure, a first interlayer dielectric layer in which the dummy gate structure is embedded, a second interlayer dielectric layer disposed over the first interlayer dielectric layer, and a resistor wire formed of a conductive material and embedded in the second interlayer dielectric layer. The resistor wire overlaps the dummy gate structure in plan view.Type: GrantFiled: August 31, 2017Date of Patent: January 1, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Hsin Hu, Yu-Chiun Lin, Yi-Hsuan Chung, Chung-Peng Hsieh, Chung-Chieh Yang, Po-Nien Chen
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Publication number: 20170365552Abstract: A semiconductor device includes a dummy fin structure disposed over a substrate, a dummy gate structure disposed over a part of the dummy fin structure, a first interlayer dielectric layer in which the dummy gate structure is embedded, a second interlayer dielectric layer disposed over the first interlayer dielectric layer, and a resistor wire formed of a conductive material and embedded in the second interlayer dielectric layer. The resistor wire overlaps the dummy gate structure in plan view.Type: ApplicationFiled: August 31, 2017Publication date: December 21, 2017Inventors: Chia-Hsin HU, Yu-Chiun LIN, Yi-Hsuan CHUNG, Chung-Peng HSIEH, Chung-Chieh YANG, Po-Nien CHEN
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Patent number: 9773731Abstract: A semiconductor device includes a dummy fin structure disposed over a substrate, a dummy gate structure disposed over a part of the dummy fin structure, a first interlayer dielectric layer in which the dummy gate structure is embedded, a second interlayer dielectric layer disposed over the first interlayer dielectric layer, and a resistor wire formed of a conductive material and embedded in the second interlayer dielectric layer. The resistor wire overlaps the dummy gate structure in plan view.Type: GrantFiled: January 28, 2016Date of Patent: September 26, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Hsin Hu, Yu-Chiun Lin, Yi-Hsuan Chung, Chung-Peng Hsieh, Chung-Chieh Yang, Po-Nien Chen
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Publication number: 20170221821Abstract: A semiconductor device includes a dummy fin structure disposed over a substrate, a dummy gate structure disposed over a part of the dummy fin structure, a first interlayer dielectric layer in which the dummy gate structure is embedded, a second interlayer dielectric layer disposed over the first interlayer dielectric layer, and a resistor wire formed of a conductive material and embedded in the second interlayer dielectric layer. The resistor wire overlaps the dummy gate structure in plan view.Type: ApplicationFiled: January 28, 2016Publication date: August 3, 2017Inventors: Chia-Hsin HU, Yu-Chiun LIN, Yi-Hsuan CHUNG, Chung-Peng HSIEH, Chung-Chieh YANG, Po-Nien CHEN