Patents by Inventor Yi-Hsuan Liu

Yi-Hsuan Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11711056
    Abstract: A method using a phase locked loop (PLL) includes receiving a reference frequency. The method further includes generating a control signal based on the reference frequency. The method further includes adjusting an output signal based on the control signal. Adjusting the output signal includes operating a plurality of switches in response to the control signal, wherein operating the plurality of switches comprises selectively electrically connecting a first ground plane to a first floating plane, wherein the first floating plane is between the first ground plane and the signal line, and the first floating plane is a same distance from a substrate as the first ground plane.
    Type: Grant
    Filed: May 23, 2022
    Date of Patent: July 25, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Hsuan Liu, Hsieh-Hung Hsieh, Chewn-Pu Jou, Fu-Lung Hsueh
  • Publication number: 20220286087
    Abstract: A method using a phase locked loop (PLL) includes receiving a reference frequency. The method further includes generating a control signal based on the reference frequency. The method further includes adjusting an output signal based on the control signal. Adjusting the output signal includes operating a plurality of switches in response to the control signal, wherein operating the plurality of switches comprises selectively electrically connecting a first ground plane to a first floating plane, wherein the first floating plane is between the first ground plane and the signal line, and the first floating plane is a same distance from a substrate as the first ground plane.
    Type: Application
    Filed: May 23, 2022
    Publication date: September 8, 2022
    Inventors: Yi-Hsuan LIU, Hsieh-Hung HSIEH, Chewn-Pu JOU, Fu-Lung HSUEH
  • Patent number: 11404361
    Abstract: A package structure and a method for fabricating the same are provided. An electronic component such as a sensing chip and a conductive element such as a bonding wire are mounted to a carrier, encapsulated by an encapsulant, and electrically connected through a conductive layer. As such, the electronic component can further be electrically connected to the carrier through the conductive layer and the conductive element. Therefore, the sensing chip can be packaged through current packaging processes, thereby reducing the fabrication cost, shortening the fabrication time and improving the product yield.
    Type: Grant
    Filed: November 12, 2020
    Date of Patent: August 2, 2022
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Shao-Tzu Tang, Jia-Fong Yeh, Yi-Hsuan Liu, Mei-Chi Chen, Ying-Chou Tsai
  • Patent number: 11362624
    Abstract: A varainductor includes a signal line over a substrate. The varainductor further includes a first ground plane over the substrate. The varainductor further includes a first floating plane over the substrate, wherein the first floating plane is between the first ground plane and the signal line, and the first floating plane is a same distance from the substrate as the first ground plane. The varainductor further includes a first transistor configured to selectively electrically connect the first ground plane to the first floating plane. The varainductor further includes a second transistor configured to selectively electrically connect the first ground plane to the first floating plane, wherein a gate of the first transistor is connected to a gate of the second transistor.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: June 14, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Hsuan Liu, Hsieh-Hung Hsieh, Chewn-Pu Jou, Fu-Lung Hsueh
  • Patent number: 11065171
    Abstract: The present invention relates to an assistive glove for daily activities of stroke patient which comprises a main body, a first pulling member, a second pulling member, and plural circular strings. The main body comprises a thumb sleeve, at least one finger sleeve a palm portion connected to the thumb sleeve and the at least one finger sleeve by one side and a wrist portion connected to another side of the palm portion. The first pulling member and the second pulling member are disposed on the palm portion and having a first hook and at least one second hook corresponding to the thumb sleeve and the at least one finger sleeve. The plural circular strings are hung on the first hook and the at least one second hook and fixed to the thumb sleeve and the at least one finger sleeve respectively.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: July 20, 2021
    Assignee: Southern Taiwan University of Science and Technology
    Inventors: Yang-Kun Ou, Ya-Lin Chen, Chien-Wei Fu, Yi-Hsuan Liu, Ying-Ning Tseng, You-Shan Li
  • Publication number: 20210066173
    Abstract: A package structure and a method for fabricating the same are provided. An electronic component such as a sensing chip and a conductive element such as a bonding wire are mounted to a carrier, encapsulated by an encapsulant, and electrically connected through a conductive layer. As such, the electronic component can further be electrically connected to the carrier through the conductive layer and the conductive element. Therefore, the sensing chip can be packaged through current packaging processes, thereby reducing the fabrication cost, shortening the fabrication time and improving the product yield.
    Type: Application
    Filed: November 12, 2020
    Publication date: March 4, 2021
    Inventors: Shao-Tzu Tang, Jia-Fong Yeh, Yi-Hsuan Liu, Mei-Chi Chen, Ying-Chou Tsai
  • Patent number: 10872847
    Abstract: A package structure and a method for fabricating the same are provided. An electronic component such as a sensing chip and a conductive element such as a bonding wire are mounted to a carrier, encapsulated by an encapsulant, and electrically connected through a conductive layer. As such, the electronic component can further be electrically connected to the carrier through the conductive layer and the conductive element. Therefore, the sensing chip can be packaged through current packaging processes, thereby reducing the fabrication cost, shortening the fabrication time and improving the product yield.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: December 22, 2020
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Shao-Tzu Tang, Jia-Fong Yeh, Yi-Hsuan Liu, Mei-Chi Chen, Ying-Chou Tsai
  • Publication number: 20200358398
    Abstract: A varainductor includes a signal line over a substrate. The varainductor further includes a first ground plane over the substrate. The varainductor further includes a first floating plane over the substrate, wherein the first floating plane is between the first ground plane and the signal line, and the first floating plane is a same distance from the substrate as the first ground plane. The varainductor further includes a first transistor configured to selectively electrically connect the first ground plane to the first floating plane. The varainductor further includes a second transistor configured to selectively electrically connect the first ground plane to the first floating plane, wherein a gate of the first transistor is connected to a gate of the second transistor.
    Type: Application
    Filed: July 30, 2020
    Publication date: November 12, 2020
    Inventors: Yi-Hsuan LIU, Hsieh-Hung HSIEH, Chewn-Pu JOU, Fu-Lung HSUEH
  • Patent number: 10756672
    Abstract: A varainductor includes a signal line, a ground plane, and a floating plane over a substrate. The ground plane is disposed on a side of the signal line, and the first floating plane is disposed between the ground plane and the signal line. An array of switches includes at least two switches configured to selectively electrically connect the ground plane to the floating plane.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: August 25, 2020
    Assignee: TAIWAN SEMINCONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Hsuan Liu, Hsieh-Hung Hsieh, Chewn-Pu Jou, Fu-Lung Hsueh
  • Publication number: 20200129362
    Abstract: The present invention relates to an assistive glove for daily activities of stroke patient which comprises a main body, a first pulling member, a second pulling member, and plural circular strings. The main body comprises a thumb sleeve, at least one finger sleeve a palm portion connected to the thumb sleeve and the at least one finger sleeve by one side and a wrist portion connected to another side of the palm portion. The first pulling member and the second pulling member are disposed on the palm portion and having a first hook and at least one second hook corresponding to the thumb sleeve and the at least one finger sleeve. The plural circular strings are hung on the first hook and the at least one second hook and fixed to the thumb sleeve and the at least one finger sleeve respectively.
    Type: Application
    Filed: December 13, 2018
    Publication date: April 30, 2020
    Inventors: YANG-KUN OU, YA-LIN CHEN, CHIEN-WEI FU, YI-HSUAN LIU, YING-NING TSENG, YOU-SHAN LI
  • Publication number: 20180342446
    Abstract: A package structure and a method for fabricating the same are provided. An electronic component such as a sensing chip and a conductive element such as a bonding wire are mounted to a carrier, encapsulated by an encapsulant, and electrically connected through a conductive layer. As such, the electronic component can further be electrically connected to the carrier through the conductive layer and the conductive element. Therefore, the sensing chip can be packaged through current packaging processes, thereby reducing the fabrication cost, shortening the fabrication time and improving the product yield.
    Type: Application
    Filed: September 29, 2017
    Publication date: November 29, 2018
    Inventors: Shao-Tzu Tang, Jia-Fong Yeh, Yi-Hsuan Liu, Mei-Chi Chen, Ying-Chou Tsai
  • Publication number: 20180234053
    Abstract: A varainductor includes a signal line, a ground plane, and a floating plane over a substrate. The ground plane is disposed on a side of the signal line, and the first floating plane is disposed between the ground plane and the signal line. An array of switches includes at least two switches configured to selectively electrically connect the ground plane to the floating plane.
    Type: Application
    Filed: April 11, 2018
    Publication date: August 16, 2018
    Inventors: Yi-Hsuan LIU, Hsieh-Hung HSIEH, Chewn-Pu JOU, Fu-Lung HSUEH
  • Patent number: 10031161
    Abstract: A semiconductor wafer includes a plurality of dies and at least one test probe. Each of the plurality of dies includes a radio frequency identification (RFID) tag circuit. The at least one test probe includes a plurality of probe pads. The plurality of probe pads is configured to transmit power signals and data to each of the plurality of dies, and to receive test results from each of the plurality of dies. The data are transmitted to each of the plurality of dies in a serial manner. The test results of each of the plurality of dies are also transmitted to the plurality of probe pads in a serial manner.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: July 24, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Hsiung Li, Kuang-Kai Yen, Yi-Hsuan Liu, Hsieh-Hung Hsieh, Chewn-Pu Jou, Fu-Lung Hsueh
  • Patent number: 9954488
    Abstract: A varainductor including a signal line disposed over a substrate. The varainductor further includes a first ground plane over the substrate, the first ground plane disposed on a first side of the signal line, and a second ground plane over the substrate, the second ground plane disposed on a second side of the signal line opposite the first side of the signal line. The varainductor further includes a first floating plane over the substrate, the first floating plane disposed between the first ground plane and the signal line, and a second floating plane over the substrate, the second floating plane disposed between the second ground plane and the signal line. The varainductor further includes an array of switches, the array of switches is configured to selectively connect the first ground plane to the first floating plane, and to selectively connect the second ground plane to the second floating plane.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: April 24, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Hsuan Liu, Hsieh-Hung Hsieh, Chewn-Pu Jou, Fu-Lung Hsueh
  • Patent number: 9831832
    Abstract: A low noise amplifier (LNA) includes a first transistor and a second transistor. A source of the second transistor is connected to a drain of the first transistor. The LNA further includes a feedback transformer. A gate of the first transistor is connected to a primary winding of the feedback transformer and a gate of the second transistor is connected to a secondary winding of the feedback transformer.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: November 28, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Hsuan Liu, Hsieh-Hung Hsieh, Tzu-Jin Yeh
  • Patent number: 9812251
    Abstract: A varainductor includes a spiral inductor, a ground ring, and a floating ring. The floating ring is disposed between the ground ring and the spiral inductor and surrounds a ring portion of the spiral inductor. A switching element, controlled by a switch control signal, selectively electrically connects the ground ring to the floating ring. The switching element includes one or more switches. The one or more switches are controlled by one or more signals of the switch control signal to adjust the inductance level of the varainductor.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: November 7, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Hsuan Liu, Hsieh-Hung Hsieh, Chewn-Pu Jou, Fu-Lung Hsueh
  • Publication number: 20170032891
    Abstract: A varainductor includes a spiral inductor, a ground ring, and a floating ring. The floating ring is disposed between the ground ring and the spiral inductor and surrounds a ring portion of the spiral inductor. A switching element, controlled by a switch control signal, selectively electrically connects the ground ring to the floating ring. The switching element includes one or more switches. The one or more switches are controlled by one or more signals of the switch control signal to adjust the inductance level of the varainductor.
    Type: Application
    Filed: October 12, 2016
    Publication date: February 2, 2017
    Inventors: Yi-Hsuan LIU, Hsieh-Hung HSIEH, Chewn-Pu JOU, Fu-Lung HSUEH
  • Publication number: 20160322939
    Abstract: A low noise amplifier (LNA) includes a first transistor and a second transistor. A source of the second transistor is connected to a drain of the first transistor. The LNA further includes a feedback transformer. A gate of the first transistor is connected to a primary winding of the feedback transformer and a gate of the second transistor is connected to a secondary winding of the feedback transformer.
    Type: Application
    Filed: April 30, 2015
    Publication date: November 3, 2016
    Inventors: Yi-Hsuan LIU, Hsieh-Hung HSIEH, Tzu-Jin YEH
  • Patent number: 9478344
    Abstract: A varainductor includes a spiral inductor over a substrate, the spiral inductor comprising a ring portion. The varainductor further includes a ground ring over the substrate, the ground ring surrounding at least the ring portion of the spiral inductor and a floating ring over the substrate, the floating ring disposed between the ground ring and the spiral inductor. The varainductor further includes an array of switches, the array of switches is configured to selectively connect the ground ring to the floating ring.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: October 25, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Hsuan Liu, Hsieh-Hung Hsieh, Chewn-Pu Jou, Fu-Lung Hsueh
  • Publication number: 20160187380
    Abstract: A semiconductor wafer includes a plurality of dies and at least one test probe. Each of the plurality of dies includes a radio frequency identification (RFID) tag circuit. The at least one test probe includes a plurality of probe pads. The plurality of probe pads is configured to transmit power signals and data to each of the plurality of dies, and to receive test results from each of the plurality of dies. The data are transmitted to each of the plurality of dies in a serial manner. The test results of each of the plurality of dies are also transmitted to the plurality of probe pads in a serial manner.
    Type: Application
    Filed: March 9, 2016
    Publication date: June 30, 2016
    Inventors: Tsung-Hsiung Lee, Kuang-Kai Yen, Yi-Hsuan Liu, Hsieh-Hung Hsieh, Chewn-Pu Jou, Fu-Lung Hsueh