Patents by Inventor Yi-Hsun Chung
Yi-Hsun Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240315000Abstract: A memory structure includes a substrate structure and a memory cell disposed on the substrate structure. The memory cell includes device layers stacked on the substrate structure, a word line, a first contact, and a second contact. The device layer includes a semiconductor layer, a first doped region, a second doped region, a channel region located between the first doped region and the second doped region, and a capacitor. The first and second doped regions and the channel region are disposed in the semiconductor layer. The capacitor includes a first electrode layer, a second electrode layer, and a dielectric layer located between the first and second electrode layers. The word line is disposed on a sidewall of the channel layer. The first contact is electrically connected to the first doped regions. The second contact is electrically connected to the second electrode layers. A manufacturing method thereof is provided.Type: ApplicationFiled: April 17, 2023Publication date: September 19, 2024Applicant: Winbond Electronics Corp.Inventors: Yi-Hsun Chung, Kai Jen
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Patent number: 7916519Abstract: A burn-in method for SRAMs and chips. For a memory cell of the SRAM, the SRAM burn-in method controls the control signals of the memory cell to generate current paths to pass through the memory cell, the corresponding bit-line and the corresponding bit-line-bar. The contacts/vias in the current paths are tested by providing burn-in currents to flow through the current paths, so that mismatched contacts/vias are burned by the burn-in currents. SRAMs that fail the burn-in test are abandoned after the burn-in procedure.Type: GrantFiled: February 9, 2009Date of Patent: March 29, 2011Assignee: Vanguard International Semiconductor CorporationInventors: Jui-Lung Chen, Wei-Shung Chen, Yi-Hsun Chung, Chia-Chiuan Chang
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Publication number: 20100202219Abstract: A burn-in method for SRAMs and chips. For a memory cell of the SRAM, the SRAM burn-in method controls the control signals of the memory cell to generate current paths to pass through the memory cell, the corresponding bit-line and the corresponding bit-line-bar. The contacts/vias in the current paths are tested by providing burn-in currents to flow through the current paths, so that mismatched contacts/vias are burned by the burn-in currents. SRAMs that fail the burn-in test are abandoned after the burn-in procedure.Type: ApplicationFiled: February 9, 2009Publication date: August 12, 2010Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Jui-Lung Chen, Wei-Shung Chen, Yi-Hsun Chung, Chia-Chiuan Chang
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Publication number: 20100177556Abstract: An asymmetric static random access memory (SRAM) device that includes at least one SRAM cell is provided. The SRAM cell includes the first inverter and the second inverter. The first inverter is coupled between a first power and a ground power, and includes a first output terminal coupled to a first node and a first input terminal coupled to a second node. The second inverter is coupled between the first power and the ground power, and includes a second input terminal coupled to the first node and a second output terminal coupled to the second node. When the first inverter and the second inverter receive current from the first power, the SRAM cell is programmed to a predetermined value in advance according to different conductance levels of the first inverter and the second inverter.Type: ApplicationFiled: January 9, 2009Publication date: July 15, 2010Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Jui-Lung Chen, Wei-Shung Chen, Yi-Hsun Chung, Chia-Chiuan Chang
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Patent number: 7755925Abstract: A static random access memory comprising a column driver, a row driver, a cell, and a control unit is disclosed. The column driver selects a first word line or a second word line. The row provides data to a first bit line and a second bit line. The data of the first bit line is opposite to that of the second bit line. The control unit controls the voltage of the cell. In normal mode, the voltage of the cell is equal to a second voltage. In stand-by mode, the voltage of the cell exceeds the second voltage.Type: GrantFiled: December 11, 2006Date of Patent: July 13, 2010Assignee: Vanguard International Semiconductor CorporationInventors: Jui-Lung Chen, Gia-Hua Hsieh, Yi-Hsun Chung, Chia-Chiuan Chang, Yu-Chih Yeh, Ho-Hsiang Chen
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Patent number: 7706203Abstract: A memory system is provided, comprising at least one memory unit and a source power supply circuit. Each memory unit is coupled between a source voltage and a ground voltage and accesses digital data according to a word line signal and a bit line signal. The source power supply circuit provides the source voltage to the memory units. When the memory unit is in a writing status, the source voltage is the first power voltage. When the memory unit is in a reading status, the source voltage is the second power voltage. The second power voltage equals to the first power voltage subtracted by a specific voltage for avoiding rewriting error.Type: GrantFiled: August 13, 2008Date of Patent: April 27, 2010Assignee: Vanguard International Semiconductor CorporationInventors: Jui-Lung Chen, Yi-Hsun Chung, Chia-Chiuan Chang, Wei-Shung Chen
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Publication number: 20090238023Abstract: A memory system is provided, comprising at least one memory unit and a source power supply circuit. Each memory unit is coupled between a source voltage and a ground voltage and accesses digital data according to a word line signal and a bit line signal. The source power supply circuit provides the source voltage to the memory units. When the memory unit is in a writing status, the source voltage is the first power voltage. When the memory unit is in a reading status, the source voltage is the second power voltage. The second power voltage equals to the first power voltage subtracted by a specific voltage for avoiding rewriting error.Type: ApplicationFiled: August 13, 2008Publication date: September 24, 2009Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Jui-Lung CHEN, Yi-Hsun Chung, Chia-Chiuan Chang, Wei-Shung Chen
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Publication number: 20090141534Abstract: A detection apparatus for sequentially programming a memory is provided. The detection apparatus comprises a current sensor and a programming controller. The current sensor is coupled to a programming source and a memory cell. The current sensor detects change of a programming current between the programming source and the memory cell and generates a control signal according to the detection result. The programming controller is coupled to the current sensor. The programming controller receives the control signal and generates a programming state signal.Type: ApplicationFiled: August 13, 2008Publication date: June 4, 2009Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Chia-Chiuan CHANG, Jui-Lung Chen, Yi-Hsun Chung, Wei-Shung Chen
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Publication number: 20080137398Abstract: A static random access memory comprising a column driver, a row driver, a cell, and a control unit is disclosed. The column driver selects a first word line or a second word line. The row provides data to a first bit line and a second bit line. The data of the first bit line is opposite to that of the second bit line. The control unit controls the voltage of the cell. In normal mode, the voltage of the cell is equal to a second voltage. In stand-by mode, the voltage of the cell exceeds the second voltage.Type: ApplicationFiled: December 11, 2006Publication date: June 12, 2008Inventors: Jui-Lung Chen, Gia-Hua Hsieh, Yi-Hsun Chung, Chia-Chiuan Chang, Yu-Chih Yeh, Ho-Hsiang Chen