Patents by Inventor Yi-Hsun Wu
Yi-Hsun Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240133918Abstract: In a method for obtaining the equivalent oxide thickness of a dielectric layer, a first semiconductor capacitor including a first silicon dioxide layer and a second semiconductor capacitor including a second silicon dioxide layer are provided and a modulation voltage is applied to the semiconductor capacitors to measure a first scanning capacitance microscopic signal and a second scanning capacitance microscopic signal. According to the equivalent oxide thicknesses of the silicon dioxide layers and the scanning capacitance microscopic signals, an impedance ratio is calculated. The modulation voltage is applied to a third semiconductor capacitor including a dielectric layer to measure a third scanning capacitance microscopic signal. Finally, the equivalent oxide thickness of the dielectric layer is obtained according to the equivalent oxide thickness of the first silicon dioxide layer, the first scanning capacitance microscopic signal, third scanning capacitance microscopic signal, and the impedance ratio.Type: ApplicationFiled: April 12, 2023Publication date: April 25, 2024Inventors: MAO-NAN CHANG, CHI-LUN LIU, HSUEH-LIANG CHOU, YI-SHAN WU, CHIAO-JUNG LIN, YU-HSUN HSUEH
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Patent number: 11942420Abstract: A semiconductor device includes a first gate structure extending along a first lateral direction. The semiconductor device includes a first interconnect structure, disposed above the first gate structure, that extends along a second lateral direction perpendicular to the first lateral direction. The first interconnect structure includes a first portion and a second portion electrically isolated from each other by a first dielectric structure. The semiconductor device includes a second interconnect structure, disposed between the first gate structure and the first interconnect structure, that electrically couples the first gate structure to the first portion of the first interconnect structure. The second interconnect structure includes a recessed portion that is substantially aligned with the first gate structure and the dielectric structure along a vertical direction.Type: GrantFiled: June 8, 2022Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Guo-Huei Wu, Hui-Zhong Zhuang, Chih-Liang Chen, Cheng-Chi Chuang, Shang-Wen Chang, Yi-Hsun Chiu
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Publication number: 20240077188Abstract: A light source module includes a first light source and a second light source. The first light source is configured for emitting a first light having a first wavelength, and the first light includes a first part and a second part. The second light source is configured for emitting a second light having a second wavelength. The second light source includes a first wavelength conversion layer, and the first wavelength conversion layer is configured for converting the first light into the second light. One of the first part and the second part is incident to the first wavelength conversion layer, and the other of the first part and the second part is not incident to the first wavelength conversion layer.Type: ApplicationFiled: August 22, 2023Publication date: March 7, 2024Applicant: Qisda CorporationInventors: Chih-Shiung CHIEN, Ming-Kuen LIN, Tsung-Hsun WU, Yi-Ling LO
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Publication number: 20240071656Abstract: A circuit protection device includes a first temperature sensitive resistor, a second temperature sensitive resistor, an electrically insulating multilayer, a first and second electrode layer, and at least one external electrode. The first temperature sensitive resistor and the second temperature sensitive resistor are electrically connected in parallel, and have a first upper electrically conductive layer and a second lower electrically conductive layer, respectively. The electrically insulating multilayer includes an upper insulating layer, a middle insulating layer, and a lower insulating layer. The upper insulating layer is between the first upper electrically conductive layer and the first electrode layer. The middle layer is laminated between the first temperature sensitive resistor and the second temperature sensitive resistor. The lower insulating layer is between the second lower electrically conductive layer and the second electrode layer.Type: ApplicationFiled: January 13, 2023Publication date: February 29, 2024Inventors: Chien Hui WU, Yung-Hsien CHANG, Cheng-Yu TUNG, Ming-Hsun LU, Yi-An SHA
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Publication number: 20240071330Abstract: A display device includes a display panel. The display panel has a functional display area. The functional display area includes a plurality of display pixels and a plurality of light transmitting regions. The plurality of display pixels are around by the plurality of the light transmitting regions. A boundary between one of the plurality of display pixels and one of the plurality of light transmitting regions comprises an arc segment.Type: ApplicationFiled: November 3, 2023Publication date: February 29, 2024Applicant: Innolux CorporationInventors: Chia-Hao Tsai, Ming-Jou Tai, Yi-Shiuan Cherng, Yu-Shih Tsou, You-Cheng Lu, Yung-Hsun Wu
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Publication number: 20230261463Abstract: An electrostatic discharge protection circuit includes an electrostatic discharge clamp between a first rail and a second rail, a trigger device configured to activate the electrostatic discharge clamp in response to an electrostatic discharge event, and a charge dissipation element between the first rail and the second rail to dissipate a residual charge at an input of the trigger device.Type: ApplicationFiled: April 24, 2023Publication date: August 17, 2023Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Ming-Fang Lai, Yi-Hsun Wu, Ching-Yun Chang
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Patent number: 11664657Abstract: An electrostatic discharge protection circuit includes an electrostatic discharge clamp between a first rail and a second rail, a trigger device configured to activate the electrostatic discharge clamp in response to an electrostatic discharge event, and a charge dissipation element between the first rail and the second rail to dissipate a residual charge at an input of the trigger device.Type: GrantFiled: April 1, 2022Date of Patent: May 30, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Fang Lai, Yi-Hsun Wu, Ching-Yun Chang
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Publication number: 20220224109Abstract: An electrostatic discharge protection circuit includes an electrostatic discharge clamp between a first rail and a second rail, a trigger device configured to activate the electrostatic discharge clamp in response to an electrostatic discharge event, and a charge dissipation element between the first rail and the second rail to dissipate a residual charge at an input of the trigger device.Type: ApplicationFiled: April 1, 2022Publication date: July 14, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Fang Lai, Yi-Hsun Wu, Ching-Yun Chang
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Patent number: 11296502Abstract: An electrostatic discharge protection circuit includes an electrostatic discharge clamp between a first rail and a second rail, a trigger device configured to activate the electrostatic discharge clamp in response to an electrostatic discharge event, and a charge dissipation element between the first rail and the second rail to dissipate a residual charge at an input of the trigger device.Type: GrantFiled: July 22, 2020Date of Patent: April 5, 2022Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Ming-Fang Lai, Yi-Hsun Wu, Ching-Yun Chang
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Publication number: 20220029413Abstract: An electrostatic discharge protection circuit includes an electrostatic discharge clamp between a first rail and a second rail, a trigger device configured to activate the electrostatic discharge clamp in response to an electrostatic discharge event, and a charge dissipation element between the first rail and the second rail to dissipate a residual charge at an input of the trigger device.Type: ApplicationFiled: July 22, 2020Publication date: January 27, 2022Inventors: Ming-Fang Lai, Yi-Hsun Wu, Ching-Yun Chang
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Patent number: 7672101Abstract: A system includes a driving device operating at first supply voltage Vdd1 and having a CMOS output. A driven devise operates at a second supply voltage Vdd2 lower than the first supply voltage Vdd1, and has a CMOS input with an NMOS pull-down transistor. A protection circuit includes a first resistor coupled to the CMOS output of the driving device and a gate of the NMOS pull-down transistor. A parasitic NPN bipolar junction transistor has a drain connected to the gate of the NMOS pull-down transistor sad a source coupled to a lower-voltage supply rail VSS. A second resistor connects a gate of the parasitic NPN bipolar junction transistor to Vss. The second resistor has a resistance sized for controlling a trigger voltage of the parasitic NPN bipolar junction transistor for protecting a gate oxide layer of the NMOS pull-down transistor from an electrostatic discharge.Type: GrantFiled: September 10, 2007Date of Patent: March 2, 2010Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shu-Huei Lin, Chong-Gim Gan, Yi-Hsun Wu, Yu-Chang Lin
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Patent number: 7583484Abstract: A sensor for electrostatic discharge (ESD) protection includes a voltage divider and a device coupled thereto. The sensor is coupled to an input terminal of the sensor, wherein a voltage drop occurs across the voltage divider and a high state voltage is generated at an output terminal of the sensor when an ESD voltage pulse is applied to the input terminal of the sensor. The device maintains the high state voltage at the output terminal of the sensor, while the ESD voltage pulse is applied to the input terminal of the sensor. A method for ESD protection includes the step of pulling down a gate terminal of a MOS transistor of an ESD circuit to a low state voltage when an ESD pulse is sensed.Type: GrantFiled: August 20, 2003Date of Patent: September 1, 2009Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Hsun Wu, Jian-Hsing Lee
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Patent number: 7518843Abstract: An ESD protection circuit includes a silicon controlled rectifier coupled between a circuit pad and ground for bypassing an ESD current from the circuit pad during an ESD event. An MOS transistor, having a source shared with the silicon controlled rectifier, is coupled between the pad and ground for reducing a trigger voltage of the silicon controlled rectifier during the ESD event. The silicon controlled rectifier has a first diode serially connected to a second diode in an opposite direction, between the pad and the shared source of the MOS transistor, for functioning as a bipolar transistor. In a layout view, a first area for placement of the first and second diodes is interposed between at least two separate sets of second areas for placement of the MOS transistor.Type: GrantFiled: May 19, 2005Date of Patent: April 14, 2009Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Hsun Wu, Jian-Hsing Lee
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Patent number: 7508639Abstract: Input/output devices with robustness of ESD protection are provided. An input/output device comprises an input/output pad, a first NMOS transistor, a second NMOS transistor and an ESD detector. The first NMOS transistor comprises a first drain, a first source and a first gate, wherein the first source and the first gate are coupled to a first ground power rail, and the first drain to the input/output pad. The second NMOS transistor comprises a second drain, a second source and a second gate, wherein the second source is coupled to the first ground power rail, the second drain to the input/output pad, and the second gate to a first pre-driver. When an ESD event is detected, the ESD detector makes the first pre-driver couple the second gate to the first ground power rail, thereby the first and second transistors evenly discharge ESD current.Type: GrantFiled: December 19, 2005Date of Patent: March 24, 2009Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Hsun Wu, Jian-Hsing Lee, Shui-Hung Chen
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Publication number: 20090067105Abstract: A system includes a driving device operating at first supply voltage Vdd1 and having a CMOS output. A driven devise operates at a second supply voltage Vdd2 lower than the first supply voltage Vdd1, and has a CMOS input with an NMOS pull-down transistor. A protection circuit includes a first resistor coupled to the CMOS output of the driving device and a gate of the NMOS pull-down transistor. A parasitic NPN bipolar junction transistor has a drain connected to the gate of the NMOS pull-down transistor sad a source coupled to a lower-voltage supply rail VSS. A second resistor connects a gate of the parasitic NPN bipolar junction transistor to Vss. The second resistor has a resistance sized for controlling a trigger voltage of the parasitic NPN bipolar junction transistor for protecting a gate oxide layer of the NMOS pull-down transistor from an electrostatic discharge.Type: ApplicationFiled: September 10, 2007Publication date: March 12, 2009Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shu-Huei Lin, Chong-Gim Gan, Yi-Hsun Wu, Yu-Chang Lin
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Patent number: 7465994Abstract: A layout structure for an ESD protection circuit includes a first MOS device area having a first and second doped regions of the same polarity disposed at two sides of a first conductive gate layer, and a third doped region disposed along the first doped region at one side of the first conductive gate layer. The third doped region has a polarity different from that of the first and second doped regions, such that the third doped region and the second doped region form a diode for enhancing dissipation of ESD current during a negative ESD event.Type: GrantFiled: August 29, 2006Date of Patent: December 16, 2008Assignee: Taiwan Semiconductor Manufacturing Co.Inventors: Kuo-Feng Yu, Jian-Hsing Lee, Yi-Hsun Wu, C.S Tang
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Patent number: 7462885Abstract: An electrostatic discharge-protected MOS structure is disclosed. An electrostatic discharge-protected MOS structure includes a semiconductor substrate of a first type, a first well of the first type formed in the semiconductor substrate, and a second well of a second type disposed adjacent to the first well. The MOS structure further includes a source region, a drain region, and an oxide layer and a polysilicon layer for forming a gate electrode of the MOS structure. In addition, the MOS structure includes a parasitic SCR comprising at least a parasitic NPN bipolar transistor and a buried layer of the second type interposed between the second well and the semiconductor substrate. The buried layer functions to lower a resistance of the semiconductor substrate during an ESD event so that ESD currents generated by the parasitic SCR are dissipated through the buried layer and the semiconductor substrate, thereby protecting the MOS structure.Type: GrantFiled: November 30, 2006Date of Patent: December 9, 2008Assignee: Taiwan Semiconductor Manufacturing Co.Inventors: Shui-Hung Chen, Jian-Hsing Lee, Yi-Hsun Wu, D. J. Perng, Anthony Oates
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Patent number: 7420793Abstract: A circuit system is disclosed for protecting a capacitor coupled between a voltage supply node and a complementary voltage supply node from an ESD. The circuit system includes at least one NMOS transistor having a drain coupled to the voltage supply node, a source and a gate together coupled to the complementary voltage supply node, and at least one diode chain having one or more diodes serially coupled between the voltage supply node and the complementary voltage supply node. During an ESD event, the diode chain and the NMOS transistor dissipate an ESD current from the voltage supply node to the complementary voltage supply node, thereby protecting the capacitor from ESD induced damages.Type: GrantFiled: January 12, 2006Date of Patent: September 2, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shao-Chang Huang, Jian-Hsing Lee, Yi-Hsun Wu, Jiaw-Ren Shih
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Patent number: 7420250Abstract: Provided are an electrostatic discharge (ESD) protection device and a method for making such a device. In one example, the ESD protection device includes a Zener diode region formed in a substrate and an N-type metal oxide semiconductor (NMOS) device formed adjacent to the Zener diode region. The Zener diode region has two doped regions, a gate with a grounded potential positioned between the two doped regions, and two light doped drain (LDD) features formed in the substrate. One of the LDD features is positioned between each of the two doped regions and the gate. The NMOS device includes a source and a drain formed in the substrate and a second gate positioned between the source and the drain.Type: GrantFiled: August 25, 2005Date of Patent: September 2, 2008Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shu-Chuan Lee, Ming-Hsiang Song, Shao-Chang Huang, Yi-Hsun Wu, Kuo-Feng Yu, Jian-Hsing Lee, Tong-Chern Ong
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Publication number: 20080173945Abstract: A semiconductor device formed in a semiconductor substrate for dissipating electrostatic discharge and/or accumulated charge in an integrated circuit is provided. In one embodiment, the device comprises a semiconductor substrate; a plurality of layers of metal lines formed overlying the substrate; a plurality of via plugs through intermetal dielectric layers between the layers of metal lines and wherein the via plugs interconnect the metal lines; and a dummy pad formed over the plurality of layers of metal lines, the dummy pad having a diode connected thereto and to ground for providing a discharge path for the electrostatic discharge and/or accumulated charge.Type: ApplicationFiled: January 22, 2007Publication date: July 24, 2008Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Hsun Wu, Yan-Chih Jiang, Yu-Chang Lin, Jian-Hsing Lee, Shih-Hsorng Shen, Yu-Ting Lin, Yun-Sheng Huang