Abstract: A method includes forming a dummy gate over a semiconductor fin; forming a source/drain epitaxial structure over the semiconductor fin and adjacent to the dummy gate; depositing an interlayer dielectric (ILD) layer to cover the source/drain epitaxial structure; replacing the dummy gate with a gate structure; forming a dielectric structure to cut the gate structure, wherein a portion of the dielectric structure is embedded in the ILD layer; recessing the portion of the dielectric structure embedded in the ILD layer; after recessing the portion of the dielectric structure, removing a portion of the ILD layer over the source/drain epitaxial structure; and forming a source/drain contact in the ILD layer and in contact with the portion of the dielectric structure.

Abstract: In accordance with some embodiments, a package-on-package (PoP) structure includes a first semiconductor package having a first side and a second side opposing the first side, a second semiconductor package having a first side and a second side opposing the first side, and a plurality of inter-package connector coupled between the first side of the first semiconductor package and the first side of the second semiconductor package. The PoP structure further includes a first molding material on the second side of the first semiconductor package. The second side of the second semiconductor package is substantially free of the first molding material.

Abstract: A semiconductor device and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, a fin base disposed on the substrate, nanostructured channel regions disposed on a first portion of the fin base, a gate structure surrounding the nanostructured channel regions, a source/drain (S/D) region disposed on a second portion of the fin base, and an isolation structure disposed between the S/D region and the second portion of the fin base. The isolation structure includes an undoped semiconductor layer disposed on the second portion of the fin base, a silicon-rich dielectric layer disposed on the undoped semiconductor layer, and an air spacer disposed on the silicon-rich dielectric layer.

Abstract: A method for manufacturing a device may include providing an ultra-high voltage (UHV) component that includes a source region and a drain region, and forming an oxide layer on a top surface of the UHV component. The method may include connecting a low voltage terminal to the source region of the UHV component, and connecting a high voltage terminal to the drain region of the UHV component. The method may include forming a shielding structure on a surface of the oxide layer provided above the drain region of the UHV component, forming a high voltage interconnection that connects to the shielding structure and to the high voltage terminal, and forming a metal routing that connects the shielding structure and the low voltage terminal.

Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.

Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above- mentioned memory device is also provided.

Abstract: A manufacturing method includes the following operations. A lens layer is formed above a substrate. A patterned hard mask layer is formed on the lens layer. The lens layer is etched to transfer a pattern of the patterned hard mask layer to the lens layer such that a plurality of lenses are defined, wherein the lens are micro-lenses or meta-surface lenses. A cladding layer is formed to cover the plurality of lenses and the substrate. Portions of the cladding layer are etched to form a first inclined sidewall and a second inclined sidewall, wherein the first inclined sidewall is above the second inclined sidewall, wherein a projection of the first inclined sidewall on the substrate is spaced apart from a projection of the second inclined sidewall on the substrate.

Abstract: A biosensor is provided. The biosensor includes a substrate, photodiodes, pixelated filters, an excitation light rejection layer and an immobilization layer. The substrate has pixels. The photodiodes are disposed in the substrate and correspond to one of the pixels, respectively. The pixelated filters are disposed on the substrate. The excitation light rejection layer is disposed on the pixelated filter. The immobilization layer is disposed on the excitation light rejection layer.

Abstract: An optical fingerprint sensor is provided. The optical fingerprint sensor includes a substrate, a plurality of light-shielding layers and a plurality of groups of microlenses. The substrate has a plurality of photoelectric conversion units disposed therein. The light-shielding layers are sequentially disposed on the substrate. Each light-shielding layer includes a plurality of apertures formed therein. Each group of microlenses is disposed above the apertures formed in an uppermost light-shielding layer and overlies one photoelectric conversion unit.

Abstract: A biosensor structure is provided. The biosensor structure includes a substrate, an insulating layer, a semiconductor layer and a gold disc. The insulating layer is disposed on the substrate. The semiconductor layer is disposed on the insulating layer, and a well is disposed in the semiconductor layer. The gold disc is disposed at bottom of the well.

Abstract: A sensor device is provided. The sensor device includes a first substrate, a second substrate, a flow channel and a first reaction group. The second substrate is disposed opposite the first substrate. The flow channel is disposed between the first substrate and the second substrate, and the flow channel includes a fluidic boundary. The first reaction group is disposed on the first substrate and includes a first reaction site, a second reaction site and a third reaction site. The first reaction site is closer to the fluidic boundary than the second reaction site, and a size of the first reaction site is greater than or equal to a size of the second reaction site. The second reaction site is closer to the fluidic boundary than the third reaction site, and the size of the second reaction site is greater than a size of the third reaction site.

Abstract: A method for testing mass-produced PCBs and other electronic components more efficiently, the method includes setting testing parameters based on historical test data and a target decision index, obtaining a first specified number of the target objects to have the full test, and calculating a first yield based on the current test result. The method determine whether the first yield is less than the first yield threshold yield, and obtaining a second specified number of the target objects from the remaining target objects to have the full test, and calculate a second yield when the first yield is larger than or equal to the first yield threshold value. The method further determine whether the second yield is less than the second yield threshold value according to a second comparing command and select some of the remaining target objects to have a sampling test.

Abstract: A method for testing mass-produced PCBs and other electronic components more efficiently, the method includes setting testing parameters based on historical test data and a target decision index, obtaining a first specified number of the target objects to have the full test, and calculating a first yield based on the current test result. The method determine whether the first yield is less than the first yield threshold yield, and obtaining a second specified number of the target objects from the remaining target objects to have the full test, and calculate a second yield when the first yield is larger than or equal to the first yield threshold value. The method further determine whether the second yield is less than the second yield threshold value according to a second comparing command and select some of the remaining target objects to have a sampling test.

Abstract: An optical fingerprint sensor is provided. The optical fingerprint sensor includes a substrate, a plurality of light-shielding layers and a plurality of groups of microlenses. The substrate has a plurality of photoelectric conversion units disposed therein. The light-shielding layers are sequentially disposed on the substrate. Each light-shielding layer includes a plurality of apertures formed therein. Each group of microlenses is disposed above the apertures formed in an uppermost light-shielding layer and overlies one photoelectric conversion unit.

Abstract: A biosensor is provided. The biosensor includes a substrate, photodiodes, pixelated filters, an excitation light rejection layer and an immobilization layer. The substrate has pixels. The photodiodes are disposed in the substrate and correspond to one of the pixels, respectively. The pixelated filters are disposed on the substrate. The excitation light rejection layer is disposed on the pixelated filter. The immobilization layer is disposed on the excitation light rejection layer.