Abstract: A device includes a semiconductor channel region over a substrate, a shallow trench isolation (STI) region in the substrate, a gate structure over the semiconductor channel region. The semiconductor channel region has a channel top higher than a top surface of the STI region by a first height. The device further includes a first source/drain epitaxy structure and a second source/drain epitaxy structure respectively at opposite sides of the gate structure, and a first dielectric fin sidewall structure and a second dielectric fin sidewall structure on opposite sides of the first source/drain epitaxy structure, respectively. A top of the first dielectric fin sidewall structure is higher than the top surface of the STI region by a second height. The second height is at most half the first height.

Abstract: A method includes forming a gate stack on a first portion of a semiconductor fin, removing a second portion of the semiconductor fin to form a recess, and forming a source/drain region starting from the recess. The formation of the source/drain region includes performing a first epitaxy process to grow a first semiconductor layer, wherein the first semiconductor layer has straight-and-vertical edges, and performing a second epitaxy process to grow a second semiconductor layer on the first semiconductor layer. The first semiconductor layer and the second semiconductor layer are of a same conductivity type.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a metal gate on a substrate, a spacer around the metal gate, and a first interlayer dielectric (ILD) layer around the spacer, performing a plasma treatment process to transform the spacer into a first bottom portion and a first top portion, performing a cleaning process to remove the first top portion, and forming a second ILD layer on the metal gate and the first ILD layer.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a metal gate on a substrate, a spacer around the metal gate, and a first interlayer dielectric (ILD) layer around the spacer, performing a plasma treatment process to transform the spacer into a first bottom portion and a first top portion, performing a cleaning process to remove the first top portion, and forming a second ILD layer on the metal gate and the first ILD layer.

Abstract: A device includes a semiconductor substrate, a semiconductor fin, a gate structure, a first source/drain epitaxy structure, a second source/drain epitaxy structure, a first dielectric fin sidewall structure, a second dielectric fin sidewall structure. The semiconductor fin is over the semiconductor substrate. The semiconductor fin includes a channel portion and recessed portions on opposite sides of the channel portion. The gate structure is over the channel portion of the semiconductor fin. The first source/drain epitaxy structure and the second source/drain epitaxy structure are over the recessed portions of the semiconductor fin, respectively. The first source/drain epitaxy structure has a round surface. The first dielectric fin sidewall structure and the second dielectric fin sidewall structure are on opposite sides of the first source/drain epitaxy structure. The round surface of the first source/drain epitaxy structure is directly above the first dielectric fin sidewall structure.

Abstract: A method includes forming a gate stack on a first portion of a semiconductor fin, removing a second portion of the semiconductor fin to form a recess, and forming a source/drain region starting from the recess. The formation of the source/drain region includes performing a first epitaxy process to grow a first semiconductor layer, wherein the first semiconductor layer has straight-and-vertical edges, and performing a second epitaxy process to grow a second semiconductor layer on the first semiconductor layer. The first semiconductor layer and the second semiconductor layer are of a same conductivity type.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a metal gate on a substrate, a spacer around the metal gate, and a first interlayer dielectric (ILD) layer around the spacer, performing a plasma treatment process to transform the spacer into a first bottom portion and a first top portion, performing a cleaning process to remove the first top portion, and forming a second ILD layer on the metal gate and the first ILD layer.

Abstract: A UE performs up to a threshold number of attempts to transmit a default capability message to a base station, the default capability message representing a default set of CA combinations supported by the UE. If transmission is unsuccessful, the UE switches to a compact capability mode in which the UE attempts to transmit compacted UE capability messages representing successively smaller subsets of the default set of CA combinations until either a capability message is successfully received by the base station or a second threshold number of unsuccessful transmission attempts is performed. To facilitate configuration of an initial compacted capability message, the UE maintains a PC list that lists one or more cells that have been identified previously as incapable of receiving default-sized capability messages and that further identifies a representation of a limited subset of CA combinations to include in capability messages sent to a corresponding listed cell.

Abstract: A data storage device includes a memory device and a memory controller. The memory controller is arranged to configure a plurality of first memory blocks to receive data from a host device. The first memory blocks form at least a first superblock. When an amount of data stored in the first memory blocks reaches a specific value, the memory controller moves the data from the first memory blocks to a plurality of second memory blocks in a predetermined procedure. The second memory blocks form at least a second superblock. The second superblock includes the second memory blocks located in different memory chips. The data stored in two adjacent logical pages in the first superblock is written in two second memory blocks located in different memory chips.

Abstract: A data storage device includes a memory device and a memory controller. The memory controller is arranged to configure a plurality of first memory blocks to receive data from a host device. The first memory blocks form at least a first superblock. When an amount of data stored in the first memory blocks reaches a specific value, the memory controller moves the data from the first memory blocks to a plurality of second memory blocks in a predetermined procedure. The second memory blocks form at least a second superblock. The second superblock includes the second memory blocks located in different memory chips. The data stored in two adjacent logical pages in the first superblock is written in two second memory blocks located in different memory chips.

Abstract: A light-emitting diode (LED) protection structure includes an LED portion and a protection portion. The protection portion includes a fuse and a Zener diode connected in series. The protection portion is electrically connected to the LED portion in parallel but opposite in direction. As such, the LED protection structure can effectively protect the LEDs and the Zener diode from being damaged to thereby reduce costs.

Abstract: A light-emitting diode (LED) protection structure includes an LED portion and a protection portion. The protection portion includes a fuse and a Zener diode connected in series. The protection portion is electrically connected to the LED portion in parallel but opposite in direction. As such, the LED protection structure can effectively protect the LEDs and the Zener diode from being damaged to thereby reduce costs.