Patents by Inventor Yi-Hua Lin

Yi-Hua Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240128378
    Abstract: A semiconductor device includes a first transistor and a protection structure. The first transistor includes a gate electrode, a gate dielectric disposed on the gate electrode, and a channel layer disposed on the gate dielectric. The protection structure is laterally surrounding the gate electrode, the gate dielectric and the channel layer of the first transistor. The protection structure includes a first capping layer and a dielectric portion. The first capping layer is laterally surrounding and contacting the gate electrode, the gate dielectric and the channel layer of the first transistor. The dielectric portion is disposed on the first capping layer and laterally surrounding the first transistor.
    Type: Application
    Filed: January 30, 2023
    Publication date: April 18, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Cheng Chu, Chien-Hua Huang, Yu-Ming Lin, Chung-Te Lin
  • Publication number: 20240120203
    Abstract: A method includes forming a dummy gate over a semiconductor fin; forming a source/drain epitaxial structure over the semiconductor fin and adjacent to the dummy gate; depositing an interlayer dielectric (ILD) layer to cover the source/drain epitaxial structure; replacing the dummy gate with a gate structure; forming a dielectric structure to cut the gate structure, wherein a portion of the dielectric structure is embedded in the ILD layer; recessing the portion of the dielectric structure embedded in the ILD layer; after recessing the portion of the dielectric structure, removing a portion of the ILD layer over the source/drain epitaxial structure; and forming a source/drain contact in the ILD layer and in contact with the portion of the dielectric structure.
    Type: Application
    Filed: March 8, 2023
    Publication date: April 11, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Te-Chih HSIUNG, Yun-Hua CHEN, Bing-Sian WU, Yi-Hsuan CHIU, Yu-Wei CHANG, Wen-Kuo HSIEH, Chih-Yuan TING, Huan-Just LIN
  • Patent number: 11955460
    Abstract: In accordance with some embodiments, a package-on-package (PoP) structure includes a first semiconductor package having a first side and a second side opposing the first side, a second semiconductor package having a first side and a second side opposing the first side, and a plurality of inter-package connector coupled between the first side of the first semiconductor package and the first side of the second semiconductor package. The PoP structure further includes a first molding material on the second side of the first semiconductor package. The second side of the second semiconductor package is substantially free of the first molding material.
    Type: Grant
    Filed: October 5, 2020
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Da Tsai, Meng-Tse Chen, Sheng-Feng Weng, Sheng-Hsiang Chiu, Wei-Hung Lin, Ming-Da Cheng, Ching-Hua Hsieh, Chung-Shi Liu
  • Publication number: 20240113112
    Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.
    Type: Application
    Filed: December 1, 2023
    Publication date: April 4, 2024
    Inventors: Ryan Chia-Jen Chen, Cheng-Chung Chang, Shao-Hua Hsu, Yu-Hsien Lin, Ming-Ching Chang, Li-Wei Yin, Tzu-Wen Pan, Yi-Chun Chen
  • Patent number: 11942897
    Abstract: A crystal oscillator includes an oscillating substrate, a hollow frame, a first electrode, and a second electrode. The oscillating substrate includes a main oscillating region and a thinned region that has a thickness smaller than that of the main oscillating region. The first and second electrodes are disposed on a first surface of the oscillating substrate and a second surface opposite to the first surface, respectively. The hollow frame is disposed on the second surface. The second electrode includes a second electrode portion that has at least one opening in positional correspondence with the thinned region. A method for making the crystal oscillator is also provided herein.
    Type: Grant
    Filed: August 30, 2022
    Date of Patent: March 26, 2024
    Assignees: NATIONAL YANG MING CHIAO TUNG UNIVERSITY, AKER TECHNOLOGY CO., LTD.
    Inventors: Ray-Hua Horng, Yi-Lun Lin
  • Publication number: 20240085667
    Abstract: A photolithography projection lens, having a plurality of lens elements and a light diaphragm arranged among them, arranged along an optical axis, and comprising an object side and an image side respectively arranged at the front and rear ends of the plurality of lens elements; wherein: the diopters of the two lenses respectively near the object side and the image side must be positive; each of the lens elements is a single lens without cement; the angle between the chief rays at different image height positions and the optical axis is <1 degree, and the angle between the chief rays at different object height positions and the optical axis is <1 degree; and under the projection of 350˜450 nm wavelength light, it provide the imaging effect of precise magnification.
    Type: Application
    Filed: September 14, 2022
    Publication date: March 14, 2024
    Inventors: SHENG CHE WU, YU HUNG CHOU, YI HUA LIN, YUAN HUNG SU
  • Publication number: 20240079483
    Abstract: A semiconductor device and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, a fin base disposed on the substrate, nanostructured channel regions disposed on a first portion of the fin base, a gate structure surrounding the nanostructured channel regions, a source/drain (S/D) region disposed on a second portion of the fin base, and an isolation structure disposed between the S/D region and the second portion of the fin base. The isolation structure includes an undoped semiconductor layer disposed on the second portion of the fin base, a silicon-rich dielectric layer disposed on the undoped semiconductor layer, and an air spacer disposed on the silicon-rich dielectric layer.
    Type: Application
    Filed: March 22, 2023
    Publication date: March 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Hung LIN, I-Hsieh WONG, Tzu-Hua CHIU, Cheng-Yi PENG, Chia-Pin LIN
  • Patent number: 11923425
    Abstract: A method for manufacturing a device may include providing an ultra-high voltage (UHV) component that includes a source region and a drain region, and forming an oxide layer on a top surface of the UHV component. The method may include connecting a low voltage terminal to the source region of the UHV component, and connecting a high voltage terminal to the drain region of the UHV component. The method may include forming a shielding structure on a surface of the oxide layer provided above the drain region of the UHV component, forming a high voltage interconnection that connects to the shielding structure and to the high voltage terminal, and forming a metal routing that connects the shielding structure and the low voltage terminal.
    Type: Grant
    Filed: February 17, 2023
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Cheng Chiu, Tian Sheng Lin, Hung-Chou Lin, Yi-Min Chen, Chiu-Hua Chung
  • Publication number: 20240071953
    Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above- mentioned memory device is also provided.
    Type: Application
    Filed: November 6, 2023
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Ming Chiang, Chao-wei Li, Wei-Lun Tsai, Chia-Min Lin, Yi-Da Tsai, Sheng-Feng Weng, Yu-Hao Chen, Sheng-Hsiang Chiu, Chih-Wei Lin, Ching-Hua Hsieh
  • Publication number: 20240071954
    Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.
    Type: Application
    Filed: November 9, 2023
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Ming Chiang, Chao-wei Li, Wei-Lun Tsai, Chia-Min Lin, Yi-Da Tsai, Sheng-Feng Weng, Yu-Hao Chen, Sheng-Hsiang Chiu, Chih-Wei Lin, Ching-Hua Hsieh
  • Patent number: 11899188
    Abstract: An optical lens system includes, in order from a magnified side to a minified side, a first lens group of positive refractive power and a second lens group of positive refractive power. The first lens group includes a first lens and a second lens, and the second lens group includes a third lens and a fourth lens. One of the third lens and the fourth lens includes one aspheric surface, and each of the lenses in the optical lens system is a singlet lens. The optical lens satisfies a condition of TE(?=400)>94%, where TE(?=400) denotes an overall transmittance of all of the lenses in the optical lens system measured at a wavelength of 400 nm.
    Type: Grant
    Filed: August 8, 2022
    Date of Patent: February 13, 2024
    Assignee: YOUNG OPTICS INC.
    Inventors: Hung-You Cheng, Yu-Hung Chou, Ching-Lung Lai, Yi-Hua Lin, Wei-Hao Huang
  • Publication number: 20220382023
    Abstract: An optical lens system includes, in order from a magnified side to a minified side, a first lens group of positive refractive power and a second lens group of positive refractive power. The first lens group includes a first lens and a second lens, and the second lens group includes a third lens and a fourth lens. One of the third lens and the fourth lens includes one aspheric surface, and each of the lenses in the optical lens system is a singlet lens. The optical lens satisfies a condition of TE(?=400)>94%, where TE(?=400) denotes an overall transmittance of all of the lenses in the optical lens system measured at a wavelength of 400 nm.
    Type: Application
    Filed: August 8, 2022
    Publication date: December 1, 2022
    Inventors: Hung-You CHENG, Yu-Hung CHOU, Ching-Lung LAI, Yi-Hua LIN, Wei-Hao HUANG
  • Patent number: 11448859
    Abstract: An optical lens system using ultraviolet for imaging includes, in order from a magnified side to a minified side, a first lens group of positive refractive power and a second lens group of positive refractive power. The second lens group includes at least one cemented lens and at least one aspheric lens. The optical lens system satisfies the condition of TE(?=400)>94%, where TE(?=400) denotes an overall transmittance of all of the lenses in the optical lens system measured at a wavelength of 400 nm and is equal to a product of respective internal transmittances of all of the lenses measured at a wavelength of 400 nm.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: September 20, 2022
    Assignee: YOUNG OPTICS INC.
    Inventors: Hung-You Cheng, Yu-Hung Chou, Ching-Lung Lai, Yi-Hua Lin, Wei-Hao Huang
  • Patent number: 11350839
    Abstract: A non-contact self-injection-locked vital sign sensor is disclosed, which includes transmitting antenna, receiving antenna, self-injection-locked integrated circuit and demodulator. The self-injection-locked integrated circuit includes voltage-controlled oscillator, mixer, two amplifiers and harmonic-frequency power combiner. A frequency-multiplied signal is produced by amplifiers and harmonic-frequency power combiner then transmitted to a living body by transmitting antenna. A frequency-divided signal is produced by voltage-controlled oscillator and mixer then transmitted to voltage-controlled oscillator, then a frequency- and amplitude-modulated signal is produced by the voltage-controlled oscillator then transmitted to demodulator to produce a vital sign. So as to detect vital sign with a higher frequency to increase measurement sensitivity by using a low-cost integrated circuit process.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: June 7, 2022
    Assignee: NATIONAL TAIWAN UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Chao-Hsiung Tseng, Yi-Hua Lin
  • Patent number: 10952294
    Abstract: A driving method and driving apparatus for light emitting diodes in a keyboard are provided. The driving method includes the following steps: obtaining a first driver color data table unmatched with a key light driver array from a first memory; generating a second driver color data table matched with the key light driver array in a second memory according to an arrangement order of keys in the key light driver array and the first driver color data table; driving the key light driver array according to the second driver color data table; and driving the light emitting diodes corresponding to keys in the keyboard through the key light driver array.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: March 16, 2021
    Assignee: ITE Tech. Inc.
    Inventor: Yi-Hua Lin
  • Publication number: 20200359930
    Abstract: A non-contact self-injection-locked vital sign sensor is disclosed, which includes transmitting antenna, receiving antenna, self-injection-locked integrated circuit and demodulator. The self-injection-locked integrated circuit includes voltage-controlled oscillator, mixer, two amplifiers and harmonic-frequency power combiner. A frequency-multiplied signal is produced by amplifiers and harmonic-frequency power combiner then transmitted to a living body by transmitting antenna. A frequency-divided signal is produced by voltage-controlled oscillator and mixer then transmitted to voltage-controlled oscillator, then a frequency- and amplitude-modulated signal is produced by the voltage-controlled oscillator then transmitted to demodulator to produce a vital sign. So as to detect vital sign with a higher frequency to increase measurement sensitivity by using a low-cost integrated circuit process.
    Type: Application
    Filed: March 3, 2020
    Publication date: November 19, 2020
    Inventors: CHAO-HSIUNG TSENG, YI-HUA LIN
  • Publication number: 20200218038
    Abstract: An optical lens system using ultraviolet for imaging includes, in order from a magnified side to a minified side, a first lens group of positive refractive power and a second lens group of positive refractive power. The second lens group includes at least one cemented lens and at least one aspheric lens. The optical lens system satisfies the condition of TE(?=400)>94%, where TE(?=400) denotes an overall transmittance of all of the lenses in the optical lens system measured at a wavelength of 400 nm and is equal to a product of respective internal transmittances of all of the lenses measured at a wavelength of 400 nm.
    Type: Application
    Filed: March 17, 2020
    Publication date: July 9, 2020
    Inventors: Hung-You CHENG, Yu-Hung CHOU, Ching-Lung LAI, Yi-Hua LIN, Wei-Hao HUANG
  • Publication number: 20200178365
    Abstract: A driving method and driving apparatus for light emitting diodes in a keyboard are provided. The driving method includes the following steps: obtaining a first driver color data table unmatched with a key light driver array from a first memory; generating a second driver color data table matched with the key light driver array in a second memory according to an arrangement order of keys in the key light driver array and the first driver color data table; driving the key light driver array according to the second driver color data table; and driving the light emitting diodes corresponding to keys in the keyboard through the key light driver array.
    Type: Application
    Filed: May 16, 2019
    Publication date: June 4, 2020
    Applicant: ITE Tech. Inc.
    Inventor: Yi-Hua Lin
  • Patent number: 10656397
    Abstract: An optical lens system includes, in order from a magnified side to a minified side, a first lens group and a second lens group. The first lens group of negative refractive power has at least one aspheric surface, and the second lens group of positive refractive power has at least one aspheric surface. Each of the lenses in the optical lens system is a singlet lens, and the condition: TE(?=365)>70% is satisfied, where TE(?=365) denotes an overall transmittance of all of the lenses in the optical lens system measured at a wavelength of 365 nm.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: May 19, 2020
    Assignee: YOUNG OPTICS INC.
    Inventors: Hung-You Cheng, Yu-Hung Chou, Ching-Lung Lai, Yi-Hua Lin, Wei-Hao Huang
  • Publication number: 20160377846
    Abstract: A projection lens system includes, in order from a magnified side to a reduced side, a first lens group of positive refractive power and a second lens group of positive refractive power. The second lens group includes at least one cemented lens and at least one aspheric surface. During focusing, the first lens group remains stationary, and the second lens group is movable in a direction of an optical axis.
    Type: Application
    Filed: June 25, 2015
    Publication date: December 29, 2016
    Inventors: Ching-Lung LAI, Yi-Hua LIN, Wei-Hao HUANG