Abstract: An object of the present invention is to provide a method for producing a processed molded article containing polylactic acid and having excellent transparency and excellent heat resistance. The method for producing a processed molded article of the present invention includes the following steps: preparing a molded article that contains polylactic acid containing an L-lactic acid unit at an amount of 99.0 mol % or more based on the total constituent units of the polylactic acid or a D-lactic acid unit at an amount of 99.0 mol % or more based on the total constituent units of the polylactic acid; and impregnating the molded article with carbon dioxide.

Abstract: The problem of the present invention is to provide a biodegradable resin composition that can be easily molded in a short time, with molded bodies therefrom having appropriate flexibility. The resin composition for solving the above problem comprises 100 parts by mass of poly(butylene adipate/terephthalate) and 1-10 parts by mass of an aliphatic polyester having a certain structure. The amount of the poly(butylene adipate/terephthalate) is 80% by mass or more based on the total amount.

Abstract: A method for fabricating a semiconductor device includes forming a first mask layer, a second mask layer, and a plurality of first patterned layers on an interlayer dielectric layer and a plurality of gate structures. A plurality of first openings separate the first patterned layers with each across a source region, a drain region, and a portion of an isolation area between the source and the drain regions. The second mask layer is then patterned by etching. The method includes forming a plurality of discrete second patterned layers above the isolation areas between source and drain regions and then forming a patterned first mask layer by etching. Further, the method includes forming a plurality of contact vias to expose the source/drain regions through etching using the patterned first mask layer and second mask layer as an etch mask, and then forming a metal silicide layer on each source/drain region.

Abstract: A method for manufacturing a semiconductor device having a local interconnect structure includes providing a semiconductor substrate having a gate on an active region, a hardmask layer on the gate, and a first dielectric layer on the gate, etching the first dielectric layer to form a first interconnect trench on the active region, forming a metal silicide layer at a bottom of the first interconnect trench, forming a first metal layer filling the first interconnect trench, forming a second dielectric layer on the gate and the first interconnect trench, etching the second dielectric layer to form a second interconnect trench in a staggered pattern relative to the first interconnect trench, etching the second dielectric layer to form a third interconnect trench, forming a second metal layer in the second interconnect trench and in the third interconnect trench to form the local interconnect structure.

Abstract: An interconnect structure is provided. The interconnect structure includes a substrate; and at least a first interconnect component having a first contact region and a second interconnect component having a second contact region. The interconnect structure also includes an interlayer dielectric layer formed on the semiconductor substrate at a same layer as the first interconnect component and the second interconnect component. Further, the interconnect structure includes an interconnect line layer electrically connecting the first contact region and the second contact region formed inside the interlayer dielectric layer.

Abstract: A method for DRC verification of a design layout file comprising off-grid patterns includes identifying an off-grid pattern having one or more off-grid sides, outwardly expanding the one or more off-grid sides to adjacent grids to obtain a first on-grid pattern, inwardly contracting the expanded one or more sides of the first on-grid pattern to adjacent grids to obtain a second on-grid pattern, and performing a DRC verification on the second on-grid pattern using an existing on-grid DRC deck. The method also includes making a backup copy of the design layout file prior to converting the identified off-grid pattern into an on-grid pattern.

Abstract: A semiconductor device includes a plurality of transistor components disposed on a semiconductor substrate, and a guard ring disposed on the semiconductor substrate surrounding the transistor components. The guard ring includes a plurality of fin structures disposed in parallel on the semiconductor substrate, a plurality of first conductive connection members disposed on the fin structures and connecting at least two fin structures, and a plurality of second conductive connection members connecting at least two first conductive connection members. The first conductive connection members and the second conductive connection members are formed as one structure.

Abstract: A method for manufacturing a semiconductor device having a local interconnect structure includes providing a semiconductor substrate having a gate on an active region, a hardmask layer on the gate, and a first dielectric layer on the gate, etching the first dielectric layer to form a first interconnect trench on the active region, forming a metal silicide layer at a bottom of the first interconnect trench, forming a first metal layer filling the first interconnect trench, forming a second dielectric layer on the gate and the first interconnect trench, etching the second dielectric layer to form a second interconnect trench in a staggered pattern relative to the first interconnect trench, etching the second dielectric layer to form a third interconnect trench, forming a second metal layer in the second interconnect trench and in the third interconnect trench to form the local interconnect structure.

Abstract: A method for fabricating a semiconductor device includes forming a first mask layer, a second mask layer, and a plurality of first patterned layers on an interlayer dielectric layer and a plurality of gate structures. A plurality of first openings separate the first patterned layers with each across a source region, a drain region, and a portion of an isolation area between the source and the drain regions. The second mask layer is then patterned by etching. The method includes forming a plurality of discrete second patterned layers above the isolation areas between source and drain regions and then forming a patterned first mask layer by etching. Further, the method includes forming a plurality of contact vias to expose the source/drain regions through etching using the patterned first mask layer and second mask layer as an etch mask, and then forming a metal silicide layer on each source/drain region.

Abstract: An interconnect structure is provided. The interconnect structure includes a substrate; and at least a first interconnect component having a first contact region and a second interconnect component having a second contact region. The interconnect structure also includes an interlayer dielectric layer formed on the semiconductor substrate at a same layer as the first interconnect component and the second interconnect component. Further, the interconnect structure includes an interconnect line layer electrically connecting the first contact region and the second contact region formed inside the interlayer dielectric layer.

Abstract: An interconnect structure is provided. The interconnect structure includes a substrate; and at least a first interconnect component having a first contact region and a second interconnect component having a second contact region. The interconnect structure also includes an interlayer dielectric layer formed on the semiconductor substrate at a same layer as the first interconnect component and the second interconnect component. Further, the interconnect structure includes an interconnect line layer electrically connecting the first contact region and the second contact region formed inside the interlayer dielectric layer.

Abstract: A method for DRC verification of a design layout file comprising off-grid patterns includes identifying an off-grid pattern having one or more off-grid sides, outwardly expanding the one or more off-grid sides to adjacent grids to obtain a first on-grid pattern, inwardly contracting the expanded one or more sides of the first on-grid pattern to adjacent grids to obtain a second on-grid pattern, and performing a DRC verification on the second on-grid pattern using an existing on-grid DRC deck. The method also includes making a backup copy of the design layout file prior to converting the identified off-grid pattern into an on-grid pattern.

Abstract: A method for manufacturing one or more semiconductor devices may include the following steps: providing a dielectric layer on a substrate structure that includes a first electrode and a second electrode; providing a first mask on the dielectric layer; providing a second mask, which overlaps the first mask and has a designated structure, wherein a portion of the first mask is positioned between a first portion and a second portion of the designated structure in a layout view of a process structure that includes the first mask and the second mask; and performing a removal process through the first portion of the designated structure and through the second portion of the designated structure to form a first contact hole and a second contact hole in a remaining portion of the dielectric layer, wherein the two contact holes expose the two electrodes, respectively.

Abstract: A semiconductor device includes a plurality of transistor components disposed on a semiconductor substrate, and a guard ring disposed on the semiconductor substrate surrounding the transistor components. The guard ring includes a plurality of fin structures disposed in parallel on the semiconductor substrate, a plurality of first conductive connection members disposed on the fin structures and connecting at least two fin structures, and a plurality of second conductive connection members connecting at least two first conductive connection members. The first conductive connection members and the second conductive connection members are formed as one structure.

Abstract: A method for manufacturing one or more semiconductor devices may include the following steps: providing a dielectric layer on a substrate structure that includes a first electrode and a second electrode; providing a first mask on the dielectric layer; providing a second mask, which overlaps the first mask and has a designated structure, wherein a portion of the first mask is positioned between a first portion and a second portion of the designated structure in a layout view of a process structure that includes the first mask and the second mask; and performing a removal process through the first portion of the designated structure and through the second portion of the designated structure to form a first contact hole and a second contact hole in a remaining portion of the dielectric layer, wherein the two contact holes expose the two electrodes, respectively.

Abstract: A method is provided for fabricating a fin field-effect transistor. The method includes providing a substrate having a first region and a second region; and forming a plurality of fin structures on a surface of the substrate. The method also includes forming a first mask layer having a plurality of first openings exposing the fin structures in the first region near the second region; and removing the fin structures in the first region near the second region. Further, the method includes forming a second mask layer on the fin structures in the second region; and removing the fin structures in the first region. Further, the method also includes forming fins by etching the substrate using the fin structures in the second region as an etching mask; and forming a gate structure and source/drain regions in the fins at both sides of the gate structure.

Abstract: A method is provided for fabricating a fin field-effect transistor. The method includes providing a substrate having a first region and a second region; and forming a plurality of fin structures on a surface of the substrate. The method also includes forming a first mask layer having a plurality of first openings exposing the fin structures in the first region near the second region; and removing the fin structures in the first region near the second region. Further, the method includes forming a second mask layer on the fin structures in the second region; and removing the fin structures in the first region. Further, the method also includes forming fins by etching the substrate using the fin structures in the second region as an etching mask; and forming a gate structure and source/drain regions in the fins at both sides of the gate structure.

Abstract: An interconnect structure is provided. The interconnect structure includes a substrate; and at least a first interconnect component having a first contact region and a second interconnect component having a second contact region. The interconnect structure also includes an interlayer dielectric layer formed on the semiconductor substrate at a same layer as the first interconnect component and the second interconnect component. Further, the interconnect structure includes an interconnect line layer electrically connecting the first contact region and the second contact region formed inside the interlayer dielectric layer.