Patents by Inventor Yi-Huang Wu

Yi-Huang Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210193911
    Abstract: A memory device includes a substrate, an etch stop layer, a protective layer, and a resistance switching element. The substrate has a memory region and a logic region, and includes a metallization pattern therein. The etch stop layer is over the substrate, and has a first portion over the memory region and a second portion over the logic region. The protective layer covers the first portion of the etch stop layer. The protective layer does not cover the second portion of the etch stop layer. The resistance switching element is over the memory region, and the resistance switching element is electrically connected to the metallization pattern through the etch stop layer and the protective layer.
    Type: Application
    Filed: December 19, 2019
    Publication date: June 24, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Hsiang TSENG, Chih-Lin WANG, Yi-Huang WU
  • Patent number: 10163727
    Abstract: A device includes a semiconductor substrate, a first Metal-Oxide-Semiconductor (MOS) device, and a second MOS device of a same conductivity as the first MOS device. The first MOS device includes a first gate stack over the semiconductor substrate, and a first stressor adjacent to the first gate stack and extending into the semiconductor substrate. The first stressor and the first gate stack have a first distance. The second MOS device includes a second gate stack over the semiconductor substrate, and a second stressor adjacent to the second gate stack and extending into the semiconductor substrate. The second stressor and the second gate stack have a second distance greater than the first distance.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jelin Wang, Ching-Chen Hao, Yi-Huang Wu, Meng Yi Sun
  • Publication number: 20160027702
    Abstract: A device includes a semiconductor substrate, a first Metal-Oxide-Semiconductor (MOS) device, and a second MOS device of a same conductivity as the first MOS device. The first MOS device includes a first gate stack over the semiconductor substrate, and a first stressor adjacent to the first gate stack and extending into the semiconductor substrate. The first stressor and the first gate stack have a first distance. The second MOS device includes a second gate stack over the semiconductor substrate, and a second stressor adjacent to the second gate stack and extending into the semiconductor substrate. The second stressor and the second gate stack have a second distance greater than the first distance.
    Type: Application
    Filed: October 5, 2015
    Publication date: January 28, 2016
    Inventors: Jelin Wang, Ching-Chen Hao, Yi-Huang Wu, Meng Yi Sun
  • Patent number: 9153690
    Abstract: A device includes a semiconductor substrate, a first Metal-Oxide-Semiconductor (MOS) device, and a second MOS device of a same conductivity as the first MOS device. The first MOS device includes a first gate stack over the semiconductor substrate, and a first stressor adjacent to the first gate stack and extending into the semiconductor substrate. The first stressor and the first gate stack have a first distance. The second MOS device includes a second gate stack over the semiconductor substrate, and a second stressor adjacent to the second gate stack and extending into the semiconductor substrate. The second stressor and the second gate stack have a second distance greater than the first distance.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: October 6, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jelin Wang, Ching-Chen Hao, Yi-Huang Wu, Meng Yi Sun
  • Patent number: 8741726
    Abstract: Methods are disclosed of forming and removing a reacted layer on a surface of a recess to provide mechanisms for improving thickness uniformity of a semiconductor material formed in the recess. The improved thickness uniformity in turn improves the uniformity of device performance.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: June 3, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Te Lin, Chih-Lin Wang, Yi-Huang Wu, Tzong-Sheng Chang
  • Publication number: 20130228826
    Abstract: A device includes a semiconductor substrate, a first Metal-Oxide-Semiconductor (MOS) device, and a second MOS device of a same conductivity as the first MOS device. The first MOS device includes a first gate stack over the semiconductor substrate, and a first stressor adjacent to the first gate stack and extending into the semiconductor substrate. The first stressor and the first gate stack have a first distance. The second MOS device includes a second gate stack over the semiconductor substrate, and a second stressor adjacent to the second gate stack and extending into the semiconductor substrate. The second stressor and the second gate stack have a second distance greater than the first distance.
    Type: Application
    Filed: March 1, 2012
    Publication date: September 5, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jelin Wang, Ching-Chen Hao, Yi-Huang Wu, Meng Yi Sun
  • Publication number: 20130143391
    Abstract: Methods are disclosed of forming and removing a reacted layer on a surface of a recess to provide mechanisms for improving thickness uniformity of a semiconductor material formed in the recess. The improved thickness uniformity in turn improves the uniformity of device performance.
    Type: Application
    Filed: December 1, 2011
    Publication date: June 6, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Te LIN, Chih-Lin WANG, Yi-Huang WU, Tzong-Sheng CHANG
  • Patent number: 5903035
    Abstract: An FET semiconductor substrate includes source/drain regions with an outer buried contact region overlapping the drain region, a gate oxide layer, and a polysilicon layer over the gate oxide layer. An inner buried contact opening through the polysilicon and the gate oxide layer reaches down to the substrate over the outer buried contact region. An inner buried contact region, within the outer buried contact region, is self-aligned with the buried contact opening. A second polysilicon layer formed over the gate oxide layer reaches down through the buried contact opening into contact with the inner buried contact region. An interconnect and a gate electrode are formed from the polysilicon layers. Source/drain regions are self-aligned with the gate electrode and whereas the drain region is spaced from the inner buried contact region, the outer buried contact region interconnects the drain region with the inner buried contact region.
    Type: Grant
    Filed: September 26, 1997
    Date of Patent: May 11, 1999
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Huang Wu, Der-Chen Chen
  • Patent number: 5705437
    Abstract: A method of forming an FET device starts by forming a sacrificial layer over a semiconductor substrate and an outer buried contact region is produced by ion implantation into the substrate, followed by stripping the sacrificial layer, forming a gate oxide layer, and depositing polysilicon over the gate oxide layer. Then, etch an inner buried contact opening through the polysilicon and the gate oxide layer down to the substrate over the outer buried contact region forming an etched buried contact opening. Implant dopant into the substrate through the inner buried contact opening in the second mask to dope the substrate forming the inner buried contact region within the outer buried contact region self-aligned with the etched buried contact opening. Form a blanket, second polysilicon layer over the gate oxide layer reaching down through the etched buried contact opening into electrical and mechanical contact with the inner buried contact region.
    Type: Grant
    Filed: September 25, 1996
    Date of Patent: January 6, 1998
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Huang Wu, Der-Chen Chen