Patents by Inventor Yi-Hui Wang

Yi-Hui Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12105892
    Abstract: An electronic device includes: at least one connection interface, to receive an external signal. A first signal switching multiplexer is connected to the connection interface. A laptop system is connected to the first signal switching multiplexer, to operate in a laptop mode. A drawing board system is connected to the first signal switching multiplexer, to operate in a drawing board mode and an independent screen mode. A switching switch generates a switching signal and transmits it to the first signal switching multiplexer, the laptop system, and the drawing board system, to select the laptop mode, the drawing board mode, or the independent screen mode.
    Type: Grant
    Filed: August 24, 2022
    Date of Patent: October 1, 2024
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Yi-Lun Lai, Cheng-Hui Wu, Huan-Hsun Huang, Hung-Yi Lin, Yi-Ou Wang
  • Patent number: 12107549
    Abstract: An amplifier with enhanced slew rate includes an input stage including a first channel coupled to receive differential inputs and a second channel coupled to receive the differential inputs; a middle stage including a first current source coupled to receive outputs of the second channel and electrically connected to power, a second current source coupled to receive outputs of the first channel and electrically connected to ground, and a floating current source electrically connected between the first current source and the second current source; and an output stage coupled to the middle stage to generate an output voltage. A transit circuit is disposed in the input stage or the middle stage, controlled by the output stage, and configured to supply extra current during signal transition of the differential inputs, thereby enhancing the slew rate.
    Type: Grant
    Filed: March 14, 2022
    Date of Patent: October 1, 2024
    Assignee: Himax Technologies Limited
    Inventors: Yi-Lun Chiang, Jia-Hui Wang
  • Publication number: 20240268124
    Abstract: A semiconductor structure includes a substrate, a first dielectric layer on the substrate, a plurality of memory stack structures on the first dielectric layer, an insulating layer conformally covering the memory stack structures and the first dielectric layer, a second dielectric layer on the insulating layer and filling the spaces between the memory stack structures, a first interconnecting structure through the second dielectric layer, wherein a top surface of the first interconnecting structure is flush with a top surface of the second dielectric layer and higher than top surfaces of the memory stack structures, a third dielectric layer on the second dielectric layer, and a plurality of second interconnecting structures through the third dielectric layer, the second dielectric layer and the insulating layer on the top surfaces of the memory stack structures to contact the top surfaces of the memory stack structures.
    Type: Application
    Filed: April 16, 2024
    Publication date: August 8, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Yu-Ping Wang, Chen-Yi Weng, Chin-Yang Hsieh, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Jing-Yin Jhang, Chien-Ting Lin
  • Publication number: 20240260481
    Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a spacer adjacent to the MTJ, a liner adjacent to the spacer, and a first metal interconnection on the MTJ. Preferably, the first metal interconnection includes protrusions adjacent to two sides of the MTJ and a bottom surface of the protrusions contact the liner directly.
    Type: Application
    Filed: March 1, 2024
    Publication date: August 1, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Tu-Ping Wang
  • Publication number: 20240243664
    Abstract: A controller of a buck-boost conversion circuit and a mode switching method thereof are provided. The controller control operations of multiple switches of the buck-boost conversion circuit to convert an input voltage into an output voltage and provide an output current. The controller includes a slope compensation circuit, a control loop, and a mode switching circuit. The slope compensation circuit generates a slope compensation signal according to a mode switching signal of a current cycle. The control loop is coupled to the slope compensation circuit and the switches respectively, and is configured to generate multiple switch control signals according to the slope compensation signal, a feedback voltage related to the output voltage, and a current sense signal related to the output current to control the operations of the switches respectively. The mode switching circuit is coupled to the slope compensation circuit and the control loop.
    Type: Application
    Filed: December 22, 2023
    Publication date: July 18, 2024
    Applicant: uPI Semiconductor Corp.
    Inventors: Yen Hui Wang, Yi-Xian Jan, Chien Hsien Tsai, Kuo-Jen Kuo, Chao-Chung Huang, Cheng-Hsing Li
  • Patent number: 8172486
    Abstract: An engineering-purpose netted vegetation blanket including a plurality of mesh units arrayed and interwoven into rows. The mesh units each have borders loop-knitted using threads to form a double-layer structure including an upper and a lower thread layer, and a plurality of curved threads that are so woven to locate between the upper and the lower thread layer and be sequentially arrayed and extended between two adjacent ones of the borders while protruding from a plane defined by the borders. The mesh units are so arrayed that the mesh units in any two adjacent rows are in staggered relation, such that a void is formed between any two adjacent mesh units.
    Type: Grant
    Filed: September 11, 2009
    Date of Patent: May 8, 2012
    Assignee: Seven States Enterprise Co., Ltd.
    Inventor: Yi-Hui Wang
  • Publication number: 20110064528
    Abstract: An engineering-purpose netted vegetation blanket includes a plurality of mesh units arrayed and interwoven into rows. The mesh units each have borders loop-knitted using thick threads to form a double-layer structure including an upper and a lower thick-thread layer, and a plurality of curved thin threads that are so woven to locate between the upper and the lower thick-thread layer and be sequentially arrayed and extended between two adjacent ones of the borders while protruding from a plane defined by the borders. The mesh units are so arrayed that the mesh units in any two adjacent rows are in staggered relation, such that a void is formed between any two adjacent mesh units. With these arrangements, the netted vegetation blanket is flexible and can be wound into roll, and helps in easy growth of grass and plants, preventing soil erosion and retaining compost to achieve the purpose of greening environment.
    Type: Application
    Filed: September 11, 2009
    Publication date: March 17, 2011
    Inventor: Yi-Hui Wang