Abstract: A power gating circuit of a signal processing system includes a low dropout linear regulator, a control circuit, and an output circuit. The low dropout linear regulator includes a first transistor, an operational amplifier, a first resistor, a second resistor, and an output end. The output circuit includes a fourth transistor and a step-down circuit. The control circuit controls output voltage of the output circuit according to a control signal.

Abstract: A power gating circuit of a signal processing system includes a low dropout linear regulator, a control circuit, and an output circuit. The low dropout linear regulator includes a first transistor, an operational amplifier, a first resistor, a second resistor, and an output end. The output circuit includes a fourth transistor and a step-down circuit. The control circuit controls output voltage of the output circuit according to a control signal.

Abstract: The invention provides a semiconductor device with ESD protection including a guard ring and a MOS transistor array formed in a region surrounded by the guard ring. In the invention, the MOS transistor array includes a first MOS transistor and a second MOS transistor. The first MOS transistor is closer to the guard ring than the second MOS transistor is. The channel length of the second MOS transistor is greater than that of the first MOS transistor.

Abstract: The invention provides a semiconductor device with ESD protection including a guard ring and a MOS transistor array formed in a region surrounded by the guard ring. In the invention, the MOS transistor array includes a first MOS transistor and a second MOS transistor. The first MOS transistor is closer to the guard ring than the second MOS transistor is. The channel length of the second MOS transistor is greater than that of the first MOS transistor.

Abstract: The invention provides a semiconductor device with ESD protection including a guard ring and a MOS transistor array formed in a region surrounded by the guard ring. In the invention, the MOS transistor array includes a first MOS transistor and a second MOS transistor. The first MOS transistor is closer to the guard ring than the second MOS transistor is. The channel length of the second MOS transistor is greater than that of the first MOS transistor.

Abstract: A high speed voltage level shifter for use in circuitry having core circuits operating at a very low supply voltage includes a boost circuit for producing a boosted signal in accordance with a non-inverted input signal, and a voltage shifting stage for producing an output signal in response to an inverted input signal and the boosted signal. The boost circuit translates the boosted signal into a middle voltage level when the non-inverted input signal is at logic ‘0’. When the inverted input signal and the boosted signal are both at the logic ‘0’, the voltage shifting stage provides the output signal with a high voltage level. Otherwise, the voltage shifting stage pulls down the output signal to ground when the boosted signal is at the middle voltage level and the inverted input signal is at a low voltage level equal to the very low supply voltage level.

Abstract: An input terminal of a voltage level shifter controls gates of thin oxide N-type MOS transistors with a relatively low threshold voltage. Consequently, the thin oxide N-type MOS transistor is still sufficiently turned on even when the input voltage is very low such that the voltage level shifter according to the present invention operates at high speed without distortion of the waveform of an output voltage. In order to protect the thin oxide N-type transistors, thick oxide N-type MOS transistors with gates controlled by a reference voltage level and thin oxide N-type MOS transistors with gates controlled by a relatively low voltage level are connected in series to drains of the thin oxide N-type MOS transistors to be protected. The reference voltage level is larger than the threshold voltage of the thick oxide N-type MOS transistor and equal to or smaller than a sum of twice of the relatively low voltage level and the threshold voltage of the thick oxide N-type MOS transistor.

Abstract: The invention provides a semiconductor device with ESD protection including a guard ring and a MOS transistor array formed in a region surrounded by the guard ring. In the invention, the MOS transistor array includes a first MOS transistor and a second MOS transistor. The first MOS transistor is closer to the guard ring than the second MOS transistor is. The channel length of the second MOS transistor is greater than that of the first MOS transistor.

Abstract: A high speed voltage level shifter for use in circuitry having core circuits operating at a very low supply voltage includes a boost circuit for producing a boosted signal in accordance with a non-inverted input signal, and a voltage shifting stage for producing an output signal in response to an inverted input signal and the boosted signal. The boost circuit translates the boosted signal into a middle voltage level when the non-inverted input signal is at logic ‘0’. When the inverted input signal and the boosted signal are both at the logic ‘0’, the voltage shifting stage provides the output signal with a high voltage level. Otherwise, the voltage shifting stage pulls down the output signal to ground when the boosted signal is at the middle voltage level and the inverted input signal is at a low voltage level equal to the very low supply voltage level.