Abstract: A level shifter includes a buffer circuit, a first shift circuit, and a second shift circuit. The buffer circuit provides a first signal and a first inverted signal to the first shift circuit, such that the first shift circuit provides a second signal and a second inverted signal to the second shift circuit. The second shift circuit generates a plurality of output signals according to the second signal and the second inverted signal. The first shift circuit includes a plurality of first stacking transistors and a first voltage divider circuit. The first voltage divider circuit is electrically coupled between a first system high voltage terminal and a system low voltage terminal. The first voltage divider circuit is configured to provide a first inner bias to gate terminals of the first stacking transistors.

Abstract: A level shifter includes a buffer circuit, a first shift circuit, and a second shift circuit. The buffer circuit provides a first signal and a first inverted signal to the first shift circuit, such that the first shift circuit provides a second signal and a second inverted signal to the second shift circuit. The second shift circuit generates a plurality of output signals according to the second signal and the second inverted signal. The first shift circuit includes a plurality of first stacking transistors and a first voltage divider circuit. The first voltage divider circuit is electrically coupled between a first system high voltage terminal and a system low voltage terminal. The first voltage divider circuit is configured to provide a first inner bias to gate terminals of the first stacking transistors.

Abstract: The disclosure provides a voltage adjust circuit. The voltage adjust circuit includes a buffer circuit, a bias circuit, a level shifter and a cross voltage limit circuit. The buffer circuit includes a plurality of pull-up transistors and a plurality of pull-down transistors. The pull-up transistors coupled in series between an output terminal of the circuit and a high voltage system terminal. The pull-down transistors coupled in series between the output terminal and a low voltage system terminal. The cross voltage limit circuit is configured to limit transient and static bias voltages across two terminals of the pull-up transistors or the pull-down transistors.

Abstract: The disclosure provides a voltage adjust circuit. The voltage adjust circuit includes a buffer circuit, a bias circuit, a level shifter and a cross voltage limit circuit. The buffer circuit includes a plurality of pull-up transistors and a plurality of pull-down transistors. The pull-up transistors coupled in series between an output terminal of the circuit and a high voltage system terminal. The pull-down transistors coupled in series between the output terminal and a low voltage system terminal. The cross voltage limit circuit is configured to limit transient and static bias voltages across two terminals of the pull-up transistors or the pull-down transistors.

Abstract: A level shifter includes a buffer circuit, a first shift circuit, and a second shift circuit. The buffer circuit provides a first signal and a first inverted signal to the first shift circuit, such that the first shift circuit provides a second signal and a second inverted signal to the second shift circuit. The second shift circuit generates a plurality of output signals according to the second signal and the second inverted signal. The first shift circuit includes a plurality of first stacking transistors and a first voltage divider circuit. The first voltage divider circuit is electrically coupled between a first system high voltage terminal and a system low voltage terminal. The first voltage divider circuit is configured to provide a first inner bias to gate terminals of the first stacking transistors.

Abstract: A transformer circuit and a manufacturing method thereof are proposed. The transformer circuit includes plural input modules and output modules. Each of the input modules includes a first primary coil and a second primary coil, and each of the primary coils has a first positive input terminal and a negative input terminal. The first primary coil and the second primary coil of each of the input modules are inductively coupled with each other. Each of the output modules includes a secondary coil. Each of the secondary coils includes a first terminal and a second terminal. The first terminal and the second terminal of each of the secondary coils are electrically connected to a first output port and a second output port, respectively. The first primary coil and the second primary coil of each of the input modules are inductively coupled to the secondary coil of the corresponding output module, respectively.

Abstract: A transformer circuit and a manufacturing method thereof are proposed. The transformer circuit includes plural input modules and output modules. Each of the input modules includes a first primary coil and a second primary coil, and each of the primary coils has a first positive input terminal and a negative input terminal. The first primary coil and the second primary coil of each of the input modules are inductively coupled with each other. Each of the output modules includes a secondary coil. Each of the secondary coils includes a first terminal and a second terminal. The first terminal and the second terminal of each of the secondary coils are electrically connected to a first output port and a second output port, respectively. The first primary coil and the second primary coil of each of the input modules are inductively coupled to the secondary coil of the corresponding output module, respectively.

Abstract: A modulation method includes sampling the first input signal by using the first local oscillation signal and the second local oscillation signal to generate the first sampled signal, sampling the second input signal by using the third local oscillation signal and the fourth local oscillation signal to generate the second sampled signal, sampling the second input signal by using the first local oscillation signal and the second local oscillation signal to generate the third sampled signal, sampling the first input signal by using the third local oscillation signal and the fourth local oscillation signal to generate the fourth sampled signal, adding the first sampled signal and the second sampled signal to produce the first modulation signal, adding the third sampled signal and the fourth sampled signal to generate the second modulation signal, and adding the first modulation signal and the second modulation signal to generate an output signal.

Abstract: A modulation method includes sampling the first input signal by using the first local oscillation signal and the second local oscillation signal to generate the first sampled signal, sampling the second input signal by using the third local oscillation signal and the fourth local oscillation signal to generate the second sampled signal, sampling the second input signal by using the first local oscillation signal and the second local oscillation signal to generate the third sampled signal, sampling the first input signal by using the third local oscillation signal and the fourth local oscillation signal to generate the fourth sampled signal, adding the first sampled signal and the second sampled signal to produce the first modulation signal, adding the third sampled signal and the fourth sampled signal to generate the second modulation signal, and adding the first modulation signal and the second modulation signal to generate an output signal.

Abstract: The invention proposes a system and method of a display device. When the distance between a user and the display device is too close or far, or the angle between the user and the display device slants too much, the display device sends out a command to inform the user to adjust the user's position while watching the display device. A method for the display device comprises following steps: a detecting device and an operating system calculating a relative position between the user and the display device, the operating system generating an warning command according to the relative position, a warning module receiving the warning command and afterward sending out the command, the command being sent to a display module, a motion-generating device and an audio device.

Abstract: A receiver of a GNSS system is provided. The receiver comprises two mixers and a processing circuit. The first mixer down-converts an input radio-frequency signal comprising a first GNSS signal and a second GNSS signal into a first low-frequency signal. The second mixer down-converts the input radio-frequency signal into a second low-frequency signal. The processing circuit generates at least one phase-shifted low-frequency signal according to at least the first low-frequency signal, extract signal components of the first GNSS signal by rejecting signal components of the second GNSS signal according to the second low-frequency signal and the at least one phase-shifted low-frequency signal, and extract signal components of the second GNSS signal by rejecting signal components of the first GNSS signal according to the second low-frequency signal and the at least one phase-shifted low-frequency signal. The first and second GNSS signals are situated in different frequency ranges.

Abstract: A receiver of a GNSS system is provided. The receiver comprises two mixers and a processing circuit. The first mixer down-converts an input radio-frequency signal comprising a first GNSS signal and a second GNSS signal into a first low-frequency signal. The second mixer down-converts the input radio-frequency signal into a second low-frequency signal. The processing circuit generates at least one phase-shifted low-frequency signal according to at least the first low-frequency signal, extract signal components of the first GNSS signal by rejecting signal components of the second GNSS signal according to the second low-frequency signal and the at least one phase-shifted low-frequency signal, and extract signal components of the second GNSS signal by rejecting signal components of the first GNSS signal according to the second low-frequency signal and the at least one phase-shifted low-frequency signal. The first and second GNSS signals are situated in different frequency ranges.

Abstract: An exemplary amplitude shift keying (ASM) demodulator and a radio frequency identification (RFID) system using the same are provided. The ASM demodulator is adapted to demodulate an alternating current input signal and generate a demodulated envelope signal. The ASM demodulator includes a signal input terminal group, an input rectifier circuit, a current mirror circuit electrically coupled to the input rectifier circuit, an output stage electrically coupled to the current mirror circuit, and a low pass filter electrically coupled to the output stage. The input rectifier circuit is electrically coupled to the signal input terminal group and adapted to perform a rectifying operation applied to the alternating current input signal. The input rectifier circuit includes a plurality of electrically coupled transistors and a gate electrode of each of the transistors is unconnected with a source electrode and a drain electrode itself.

Abstract: A signal source device is provided and includes a plurality of latch units, an inverter unit, and a voltage-shifting unit, which may include a capacitance unit. The plurality of latch units are substantially cascaded. The inverter unit is coupled to the latch units. The voltage-shifting unit has a first terminal coupled to the inverter unit and one of the latch units and a second terminal receiving a first input signal, for shifting a voltage level at the first terminal according to the first input signal.

Abstract: A signal source device is provided and includes a plurality of latch units, an inverter unit, and a voltage-shifting unit, which may include a capacitance unit. The plurality of latch units are substantially cascaded. The inverter unit is coupled to the latch units. The voltage-shifting unit has a first terminal coupled to the inverter unit and one of the latch units and a second terminal receiving a first input signal, for shifting a voltage level at the first terminal according to the first input signal.

Abstract: An exemplary amplitude shift keying (ASM) demodulator and a radio frequency identification (RFID) system using the same are provided. The ASM demodulator is adapted to demodulate an alternating current input signal and generate a demodulated envelope signal. The ASM demodulator includes a signal input terminal group, an input rectifier circuit, a current mirror circuit electrically coupled to the input rectifier circuit, an output stage electrically coupled to the current mirror circuit, and a low pass filter electrically coupled to the output stage. The input rectifier circuit is electrically coupled to the signal input terminal group and adapted to perform a rectifying operation applied to the alternating current input signal. The input rectifier circuit includes a plurality of electrically coupled transistors and a gate electrode of each of the transistors is unconnected with a source electrode and a drain electrode itself.

Abstract: A bias circuit includes a transistor having a control gate, a first terminal and a second terminal coupled to a ground level, a first resistor coupled to the control gate, a first capacitor coupled between an input signal and the first resistor, a diode coupled between a connection point of the first capacitor and the first resistor, and the ground level, a second capacitor coupled between the control gate and the ground level, a second resistor coupled between the control gate and the ground level, a third resistor coupled between the control gate and a predetermined voltage, a fourth resistor coupled between the predetermined voltage and the first terminal, and a fifth resistor coupled between the first terminal and a bias signal. A current through the transistor corresponds to the input signal, and the bias signal is generated according to the current through the transistor.

Abstract: A bias circuit includes a transistor having a control gate, a first terminal and a second terminal coupled to a ground level, a first resistor coupled to the control gate, a first capacitor coupled between an input signal and the first resistor, a diode coupled between a connection point of the first capacitor and the first resistor, and the ground level, a second capacitor coupled between the control gate and the ground level, a second resistor coupled between the control gate and the ground level, a third resistor coupled between the control gate and a predetermined voltage, a fourth resistor coupled between the predetermined voltage and the first terminal, and a fifth resistor coupled between the first terminal and a bias signal. A current through the transistor corresponds to the input signal, and the bias signal is generated according to the current through the transistor.