Patents by Inventor Yi Jen Su
Yi Jen Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240087861Abstract: In an embodiment, a magnetic assembly includes: an inner permeance annulus; and an outer permeance annulus connected to the inner permeance annulus via magnets, wherein the outer permeance annulus comprises a peak region with a thickness greater than other regions of the outer permeance annulus.Type: ApplicationFiled: November 17, 2023Publication date: March 14, 2024Inventors: Tsung-Jen YANG, Yi-Zhen CHEN, Chih-Pin WANG, Chao-Li SHIH, Ching-Hou SU, Cheng-Yi HUANG
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Publication number: 20240079524Abstract: A semiconductor device comprises a first semiconductor structure, a second semiconductor structure located on the first semiconductor structure, and an active layer located between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure has a first conductivity type, and includes a plurality of first layers and a plurality of second layers alternately stacked. The second semiconductor structure has a second conductivity type opposite to the first conductivity type. The plurality of first layers and the plurality of second layers include indium and phosphorus, and the plurality of first layers and the plurality of second layers respectively have a first indium atomic percentage and a second indium atomic percentage. The second indium atomic percentage is different from the first indium atomic percentage.Type: ApplicationFiled: September 6, 2023Publication date: March 7, 2024Inventors: Wei-Jen HSUEH, Shih-Chang LEE, Kuo-Feng HUANG, Wen-Luh LIAO, Jiong-Chaso SU, Yi-Chieh LIN, Hsuan-Le LIN
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Patent number: 10216963Abstract: The method, executed by at least one processor of a computer, of an encrypting or a decrypting method for an IC layout is proposed. The encrypting method comprises getting a record of an IC layout object from a database. Data of the IC layout object is appended into a byte array. The byte array is encrypted into a second byte array. Each byte of the second byte array is defined as an encryption value to create multiple encryption values. Finally, an encryption object with multiple encryption values is created on a specified layer.Type: GrantFiled: December 12, 2016Date of Patent: February 26, 2019Assignee: AnaGlobe Technology, Inc.Inventors: Yi-Jen Su, Chung-Cheng Lee, Hung Yeh Chen
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Publication number: 20180165477Abstract: The method, executed by at least one processor of a computer, of an encrypting or a decrypting method for an IC layout is proposed. The encrypting method comprises getting a record of an IC layout object from a database. Data of the IC layout object is appended into a byte array. The byte array is encrypted into a second byte array. Each byte of the second byte array is defined as an encryption value to create multiple encryption values. Finally, an encryption object with multiple encryption values is created on a specified layer.Type: ApplicationFiled: December 12, 2016Publication date: June 14, 2018Applicant: AnaGlobe Technology, Inc.Inventors: Yi-Jen Su, Chung-Cheng Lee, Hung Yeh Chen
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Patent number: 8910303Abstract: A method for manipulating security of an integrated circuit layout, comprising: rendering a PCell that is created by an original user for a successive user; providing an open access to the PCell; providing a PCell evaluator to execute evaluating steps of: getting license information from the PCell, and checking the PCell license information; and generating a layout of a sub-master by instantiating a super-master of the PCell if the PCell license information is valid, or leave the sub-master empty in a PCell view if the PCell license information is invalid.Type: GrantFiled: May 1, 2012Date of Patent: December 9, 2014Assignee: Anaglobe Technology, Inc.Inventors: Yi-Jen Su, Ying-Sung Huang
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Publication number: 20130298262Abstract: A method for manipulating security of an integrated circuit layout, comprising: rendering a PCell that is created by an original user for a successive user; providing an open access to the PCell; providing a PCell evaluator to execute evaluating steps of: getting license information from the PCell, and checking the PCell license information; and generating a layout of a sub-master by instantiating a super-master of the PCell if the PCell license information is valid, or leave the sub-master empty in a PCell view if the PCell license information is invalid.Type: ApplicationFiled: May 1, 2012Publication date: November 7, 2013Inventors: Yi-Jen SU, Ying-Sung Huang
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Patent number: 8214312Abstract: A radio frequency (RF) calibrating system and a method for calibrating RF power of communication devices are provided. The method collects RF signals transmitted from the communication devices, and generates a group of training samples by retrieving measurement data from the RF signals. The method further constructs a neural network according to the group of training samples, calibrate RF power of the communication devices using the neural network, and generate corresponding calibration results of the RF power. In addition, the method generates a frequency spectrum of the RF power according to the calibration results of the RF power, and displays the frequency spectrum on a display device of the RF calibrating system.Type: GrantFiled: July 24, 2009Date of Patent: July 3, 2012Assignee: Chi Mei Communication Systems, Inc.Inventor: Yi-Jen Su
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Patent number: 8024543Abstract: A memory management system and method for a memory system of a mobile device includes initializing memory blocks of the memory system, obtaining a peak utilization rate and an average fragmentation rate of each memory block, adjusting configuration of each memory block P1 having a maximum peak utilization rate and each memory block P2 having a minimum peak utilization rate if a preset statistical count has been reached. The method further includes adjusting a size of each memory block P3 whose peak utilization rate is greater than a preset peak utilization rate and the average fragmentation rate is a maximum, or adjusting a size of each memory block P4 whose size is less than the size of a memory block P3, and merging residual parts generated by the adjustment to form one or more memory blocks P1.Type: GrantFiled: June 7, 2009Date of Patent: September 20, 2011Assignee: Chi Mei Communications Systems, Inc.Inventor: Yi-Jen Su
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Publication number: 20100287519Abstract: A method and a system for constructing a customized layout figure group are disclosed. The method provides improved options for users to flexibly create a customized figure group design. During the layout process, the layout shape, the leaf device and the nest device with design parameters can be created with built-in figure groups, user's scripts and/or by capturing the user's existing layout.Type: ApplicationFiled: May 11, 2009Publication date: November 11, 2010Applicant: ANAGLOBE TECHNOLOGY, INC.Inventor: YI JEN SU
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Publication number: 20100169254Abstract: A radio frequency (RF) calibrating system and a method for calibrating RF power of communication devices are provided. The method collects RF signals transmitted from the communication devices, and generates a group of training samples by retrieving measurement data from the RF signals. The method further constructs a neural network according to the group of training samples, calibrate RF power of the communication devices using the neural network, and generate corresponding calibration results of the RF power. In addition, the method generates a frequency spectrum of the RF power according to the calibration results of the RF power, and displays the frequency spectrum on a display device of the RF calibrating system.Type: ApplicationFiled: July 24, 2009Publication date: July 1, 2010Applicant: CHI MEI COMMUNICATION SYSTEMS, INC.Inventor: YI-JEN SU
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Publication number: 20100131735Abstract: A memory management system and method for a memory system of a mobile device includes initializing memory blocks of the memory system, obtaining a peak utilization rate and an average fragmentation rate of each memory block, adjusting configuration of each memory block P1 having a maximum peak utilization rate and each memory block P2 having a minimum peak utilization rate if a preset statistical count has been reached. The method further includes adjusting a size of each memory block P3 whose peak utilization rate is greater than a preset peak utilization rate and the average fragmentation rate is a maximum, or adjusting a size of each memory block P4 whose size is less than the size of a memory block P3, and merging residual parts generated by the adjustment to form one or more memory blocks P1.Type: ApplicationFiled: June 7, 2009Publication date: May 27, 2010Applicant: Chi Mei Communication Systems, Inc.Inventor: Yi-Jen Su
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Publication number: 20090124264Abstract: A mobile phone capable of switching radio channels of an FM radio is provided. The mobile phone includes antennas for receiving analog signals and wireless signals. The mobile phone includes a signal conversion module for converting the analog signals to digital signals, and a channel database for storing radio channel information corresponding to LAI information of different local areas. A communication protocol processing module of the mobile phone is configured for receiving the digital signals, and for reading the LAI information of a local area where the mobile phone is located. A FM management module of the mobile phone is configured for searching the channel database to retrieve available radio channel information in the local area, synchronously monitoring if the LAI information changes, and determining if the FM radio needs to switch from one radio channel to another radio channel.Type: ApplicationFiled: August 8, 2008Publication date: May 14, 2009Applicant: CHI MEI COMMUNICATION SYSTEMS, INC.Inventor: YI-JEN SU
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Publication number: 20080010624Abstract: An integrated circuit layout method directly extracts plural primitive objects from a user's existing layout to expedite a new layout for reuse and migration and to gain the benefits of full coverage and minimal cost of layout design. The integrated circuit layout method comprises the steps of capturing a set of design parameters from a user's existing layout; capturing a plurality of primitive objects from the user's existing layout; extracting at least one leaf device from the user's existing layout; defining at least one nested device based on the leaf device; setting compaction constraints for the nested device to form a basic layout; and performing a layout task based on the basic layout.Type: ApplicationFiled: July 6, 2006Publication date: January 10, 2008Inventors: Po Huang Lin, Yi Jen Su, Miin Chih Shih
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Patent number: 7222321Abstract: A system and method for manipulating an integrated circuit layout allowing for reuse and migration. The method comprises steps of identifying objects in a geometric layout to generate a first symbolic layout, nesting a plurality of objects in the first symbolic layout to generate a first virtual device, and associating the first virtual device to generate a second symbolic layout. The method further comprises a step of modifying parameters and constraints of the first virtual device to generate a third virtual device, and a step of optimizing a second symbolic layout including the first virtual devices to generate a third symbolic layout based on the third virtual device. Consequently, the second symbolic layout can be reused. Further, the method comprises a step of updating parameters and constraints of the first virtual device based on new process rules to generate a fourth virtual device so that the second symbolic layout can be used to generate a third symbolic layout for migration.Type: GrantFiled: May 10, 2005Date of Patent: May 22, 2007Assignee: Anaglobe Technology, Inc.Inventors: Po Huang Lin, Yi Jen Su, Miin Chih Shih