Abstract: A sense amplifier circuit includes a sense amplifier, a switch and a temperature compensation circuit. The temperature compensation circuit provides a control signal having a positive temperature coefficient, based on which the switch provides reference impedance for temperature compensation. The sense amplifier includes a first input end coupled to a target bit and a second input end coupled to the switch. The sense amplifier outputs a sense amplifier signal based on the reference impedance and the impedance of the target bit.

Abstract: A bottom-pinned spin-orbit torque magnetic random access memory (SOT-MRAM) is provided in the present invention, including a substrate, a bottom electrode layer on the substrate, a magnetic tunnel junction (MTJ) on the bottom electrode layer, a spin-orbit torque (SOT) layer on the MTJ, a capping layer on the SOT layer, and an injection layer on the capping layer, wherein the injection layer is divided into individual first part and second part, and the first part and the second part are connected respectively with two ends of the capping layer.

Abstract: A memory control method and a memory storage system are provided. The method includes: in a memory closing procedure, sending, by a host system, a first control command to a memory storage device which includes a volatile memory module and a rewritable non-volatile memory module; closing, by the memory storage device, the volatile memory module in response to the first control command; and in a state where the volatile memory module is closed, maintaining, by the memory storage device, the rewritable non-volatile memory module to be operated normally.

Abstract: A temperature control method and a data storage system are disclosed. The method includes: detecting whether a memory device is in a busy status; detecting whether a temperature of the memory device is higher than a first threshold value; instructing the memory device to perform a cool down procedure in response to that the memory device is in the busy status and the temperature of the memory device is higher than the first threshold value; and instructing the memory device to stop the cool down procedure in response to that the memory device is not in the busy status and the temperature of the memory device is lower than a second threshold value.

Abstract: The present invention discloses a data storage apparatus and an operation method thereof. The data storage apparatus includes a non-volatile memory, a volatile memory coupled to the non-volatile memory, and a memory controller coupled to the non-volatile memory and the volatile memory. The memory controller is configured to perform following operations: receiving a modern standby notification from a host; and updating a second mapping table stored in the non-volatile memory according to a number of flags and a first mapping table stored in the volatile memory.

Abstract: A storage system including a random access memory, a hard disk, a non-volatile memory and a processing circuit is provided. The hard disk includes a media cache. When the processing circuit is to store data in the random access memory to the hard disk, the data in the random access memory are firstly stored to the non-volatile memory. Afterwards, the data in the non-volatile memory are directly written to a number of continuous sectors in the hard disk without being stored in the media cache of the hard disk.

Abstract: The present invention discloses a data storage apparatus and an operation method thereof. The data storage apparatus includes a non-volatile memory, a volatile memory coupled to the non-volatile memory, and a memory controller coupled to the non-volatile memory and the volatile memory. The memory controller is configured to perform following operations: receiving a modern standby notification from a host; and updating a second mapping table stored in the non-volatile memory according to a number of flags and a first mapping table stored in the volatile memory.

Abstract: A storage system including a random access memory, a hard disk, a non-volatile memory and a processing circuit is provided. The hard disk includes a media cache. When the processing circuit is to store data in the random access memory to the hard disk, the data in the random access memory are firstly stored to the non-volatile memory. Afterwards, the data in the non-volatile memory are directly written to a number of continuous sectors in the hard disk without being stored in the media cache of the hard disk.