Abstract: A semiconductor device includes a substrate, first and second fins over the substrate and extending upwardly in a first direction, an epitaxial material comprising a first portion, a second portion, and a third portion, and a conductive feature in contact with the epitaxial material. The first portion is located on the first fin, the second portion is located on the second fin, and the third portion is connected to the first and second portions. The third portion has a bottom surface bended upwardly with an apex located between the first and second fins. In a cross-sectional plane perpendicular to a lengthwise direction of the first and second fins, the bottom surface has a first straight line and a second straight line intersecting at the apex.

Abstract: An IC structure includes a first fin structure, a first epitaxial structure, first sidewall spacers, a second fin structure, a second epitaxial structure, and second sidewall spacers. The first epitaxial structure is on the first structure. The first sidewall spacers are respectively on opposite sidewalls of the first epitaxial structure. The second epitaxial structure is on the second fin structure. The second sidewall spacers are respectively on opposite sidewalls of the second epitaxial structure. A height difference between the second sidewall spacers is greater than a height difference between the first sidewall spacers.

Abstract: A device includes first and second semiconductor fins, first, second, third and fourth fin sidewall spacers, and first and second epitaxy structures. The first and second fin sidewall spacers are respectively on opposite sides of the first semiconductor fin. The third and fourth fin sidewall spacers are respectively on opposite sides of the second semiconductor fin. The first and third fin sidewall spacers are between the first and second semiconductor fins and have smaller heights than the second and fourth fin sidewall spacers. The first and second epitaxy structures are respectively on the first and second semiconductor fins and merged together.

Abstract: A method includes: providing a first gate electrode over the substrate; forming a first pair of spacers on two sides of the first gate electrode; removing the first gate electrode to form a first trench between the first pair of spacers; depositing a dielectric layer in the first trench; depositing a first layer over the dielectric layer; removing the first layer from the first trench; and depositing a work function layer over the dielectric layer in the first trench.

Abstract: A semiconductor device and method of forming the same is disclosed. The semiconductor device includes a semiconductor substrate, a first fin and a second fin extending from the semiconductor substrate, a first lower semiconductor feature over the first fin, a second lower semiconductor feature over the second fin. Each of the first and second lower semiconductor features includes a top surface bending downward towards the semiconductor substrate in a cross-sectional plane perpendicular to a lengthwise direction of the first and second fins. The semiconductor device also includes an upper semiconductor feature over and in physical contact with the first and second lower semiconductor features, and a dielectric layer on sidewalls of the first and second lower semiconductor features.

Abstract: The present disclosure describes a method for forming ultra-thin fins with a tapered bottom profile for improved structural rigidity and gate control characteristics. The method includes forming a fin structure that includes an epitaxial layer portion and a doped region portion surrounded by an isolation region so that a top section of the epitaxial layer portion is above the isolation region. The method also includes depositing a silicon-based layer on the top portion of the epitaxial layer above the isolation region and annealing the silicon-based layer to reflow the silicon-based layer. The method further includes etching the silicon-based layer and the fin structure above the isolation region to form a first bottom tapered profile in the fin structure above the isolation region and annealing the fin structure to form a second bottom tapered profile below the first bottom tapered profile and above the isolation region.

Abstract: A method includes recessing a semiconductor fin to form a recess, wherein the semiconductor fin protrudes higher than isolation regions on opposite sides of the semiconductor fin, and performing a first epitaxy to grow a first epitaxy layer extending into the recess. The first epitaxy is performed using a first process gas comprising a silicon-containing gas, silane, and a phosphorous-containing gas. The first epitaxy layer has a first phosphorous atomic percentage. The method further includes performing a second epitaxy to grow a second epitaxy layer extending into the recess and over the first epitaxy layer. The second epitaxy is performed using a second process gas comprising the silicon-containing gas, silane, and the phosphorous-containing gas. The second epitaxy layer has a second phosphorous atomic percentage higher than the first phosphorous atomic percentage.

Abstract: A method includes recessing a semiconductor fin to form a recess, wherein the semiconductor fin protrudes higher than isolation regions on opposite sides of the semiconductor fin, and performing a first epitaxy to grow a first epitaxy layer extending into the recess. The first epitaxy is performed using a first process gas comprising a silicon-containing gas, silane, and a phosphorous-containing gas. The first epitaxy layer has a first phosphorous atomic percentage. The method further includes performing a second epitaxy to grow a second epitaxy layer extending into the recess and over the first epitaxy layer. The second epitaxy is performed using a second process gas comprising the silicon-containing gas, silane, and the phosphorous-containing gas. The second epitaxy layer has a second phosphorous atomic percentage higher than the first phosphorous atomic percentage.

Abstract: The present disclosure describes a method for forming ultra-thin fins with a tapered bottom profile for improved structural rigidity and gate control characteristics. The method includes forming a fin structure that includes an epitaxial layer portion and a doped region portion surrounded by an isolation region so that a top section of the epitaxial layer portion is above the isolation region. The method also includes depositing a silicon-based layer on the top portion of the epitaxial layer above the isolation region and annealing the silicon-based layer to reflow the silicon-based layer. The method further includes etching the silicon-based layer and the fin structure above the isolation region to form a first bottom tapered profile in the fin structure above the isolation region and annealing the fin structure to form a second bottom tapered profile below the first bottom tapered profile and above the isolation region.

Abstract: A semiconductor device includes a substrate, a semiconductor feature protruding from the substrate and extending lengthwise in a first direction, an epitaxial feature directly above the semiconductor feature, and a gate stack adjacent the epitaxial feature. The epitaxial feature comprises a lower portion and an upper portion over the lower portion. The upper portion extends partially through the lower portion in a cross section perpendicular to the first direction. A topmost surface of the upper portion is substantially flat.

Abstract: A semiconductor device and method of forming the same are disclosed. The semiconductor device includes a substrate, an isolation structure over the substrate, a fin extending from the substrate, and an epitaxial feature over the fin. The epitaxial feature comprises a lower portion and an upper portion. The lower portion extends from the fin and extends above the isolation structure. The upper portion is over the lower portion. The upper portion extends partially through the lower portion in a cross section perpendicular to a lengthwise direction of the fin.

Abstract: In a method for manufacturing a semiconductor device, an isolation insulating layer is formed over a fin structure. A first portion of the fin structure is exposed from and a second portion of the fin structure is embedded in the isolation insulating layer. A dielectric layer is formed over sidewalls of the first portion of the fin structure. The first portion of the fin structure and a part of the second portion of the fin structure in a source/drain region are removed, thereby forming a trench. A source/drain epitaxial structure is formed in the trench using one of a first process or a second process. The first process comprises an enhanced epitaxial growth process having an enhanced growth rate for a preferred crystallographic facet, and the second process comprises using a modified etch process to reduce a width of the source/drain epitaxial structure.

Abstract: In a method for manufacturing a semiconductor device, an isolation insulating layer is formed over a fin structure. A first portion of the fin structure is exposed from and a second portion of the fin structure is embedded in the isolation insulating layer. A dielectric layer is formed over sidewalls of the first portion of the fin structure. The first portion of the fin structure and a part of the second portion of the fin structure in a source/drain region are removed, thereby forming a trench. A source/drain epitaxial structure is formed in the trench using one of a first process or a second process. The first process comprises an enhanced epitaxial growth process having an enhanced growth rate for a preferred crystallographic facet, and the second process comprises using a modified etch process to reduce a width of the source/drain epitaxial structure.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, an insulating stack formed over the substrate, a vertical structure formed through the insulating stack, a source/drain region formed over the vertical structure, and an isolation structure formed adjacent to the source/drain region and protruding the insulating stack. The source/drain region can include a first side surface and a second side surface. A lateral separation between the first side surface and the vertical structure can be greater than an other lateral separation between the second side surface and the vertical structure.

Abstract: A device includes a semiconductor substrate, a semiconductor fin, a gate structure, a first source/drain epitaxy structure, a second source/drain epitaxy structure, a first dielectric fin sidewall structure, a second dielectric fin sidewall structure. The semiconductor fin is over the semiconductor substrate. The semiconductor fin includes a channel portion and recessed portions on opposite sides of the channel portion. The gate structure is over the channel portion of the semiconductor fin. The first source/drain epitaxy structure and the second source/drain epitaxy structure are over the recessed portions of the semiconductor fin, respectively. The first source/drain epitaxy structure has a round surface. The first dielectric fin sidewall structure and the second dielectric fin sidewall structure are on opposite sides of the first source/drain epitaxy structure. The round surface of the first source/drain epitaxy structure is directly above the first dielectric fin sidewall structure.

Abstract: A method includes: providing a first gate electrode over the substrate; forming a first pair of spacers on two sides of the first gate electrode; removing the first gate electrode to form a first trench between the first pair of spacers; depositing a dielectric layer in the first trench; depositing a first layer over the dielectric layer; removing the first layer from the first trench; and depositing a work function layer over the dielectric layer in the first trench.

Abstract: A method for manufacturing a semiconductor device includes etching a substrate to form a semiconductor fin. An isolation structure is formed above the substrate and laterally surrounds the semiconductor fin. A fin sidewall structure is formed above the isolation structure and on a sidewall of the semiconductor fin. The semiconductor fin is recessed to expose an inner sidewall of the fin sidewall structure. A source/drain epitaxial structure is grown on the recessed semiconductor fin.

Abstract: A semiconductor device with an isolation structure and a method of fabricating the same are disclosed. The semiconductor device includes first and second fin structures disposed on a substrate and first and second pairs of gate structures disposed on the first and second fin structures. The first end surfaces of the first pair of gate structures face second end surfaces of the second pair of gate structure. The first and second end surfaces of the first and second pair of gate structures are in physical contact with first and second sidewalls of the isolation structure, respectively. The semiconductor device further includes an isolation structure interposed between the first and second pairs of gate structures. An aspect ratio of the isolation structure is smaller than a combined aspect ratio of the first pair of gate structures.

Abstract: A method includes: providing a substrate; forming a first pair of source/drain regions in the substrate; disposing an interlayer dielectric layer over the substrate, the interlayer dielectric layer having a first trench between the first pair of source/drain regions; depositing a dielectric layer in the first trench; depositing a barrier layer over the dielectric layer; performing an operation on the substrate; removing the barrier layer from the first trench to expose the dielectric layer subsequent to the operation; and depositing a work function layer over the dielectric layer in the first trench.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, an insulating stack formed over the substrate, a vertical structure formed through the insulating stack, a source/drain region formed over the vertical structure, and an isolation structure formed adjacent to the source/drain region and protruding the insulating stack. The source/drain region can include a first side surface and a second side surface. A lateral separation between the first side surface and the vertical structure can be greater than an other lateral separation between the second side surface and the vertical structure.