Patents by Inventor YI-JING LI
YI-JING LI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12020950Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. In some embodiments, a method is provided. The method includes following operations. A sacrificial gate structure is formed over a fin structure. The sacrificial gate structure includes a sacrificial gate layer and a sacrificial dielectric layer. The sacrificial gate layer is removed to form a gate trench exposing the sacrificial dielectric layer. A doped region is formed in the fin structure covered by the sacrificial dielectric layer. The sacrificial dielectric layer, a portion of the doped region and a portion of the fin structure are removed from the gate trench. An interfacial layer is formed over the fin structure in the gate trench.Type: GrantFiled: January 11, 2023Date of Patent: June 25, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: I-Sheng Chen, Siao-Jing Li, Yi-Jing Li
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Publication number: 20240194663Abstract: A semiconductor structure includes a first metal-dielectric-metal layer, a first dielectric layer, a first conductive layer, a second conductive layer, and a second dielectric layer. The first metal-dielectric-metal layer includes a plurality of first fingers, a plurality of second fingers, and a first dielectric material. The first fingers are electrically connected to a first voltage. The second fingers are electrically connected to a second voltage different from the first voltage, and the first fingers and the second fingers are arranged in parallel and staggeredly. The first dielectric material is between the first fingers and the second fingers. The first dielectric layer is over the first metal-dielectric-metal layer. The first conductive layer is over the first dielectric layer. The second conductive layer is over the first conductive layer. The second dielectric layer is between the first conductive layer and the second conductive layer.Type: ApplicationFiled: February 21, 2024Publication date: June 13, 2024Inventors: I-SHENG CHEN, YI-JING LI, CHIA-MING HSU, WAN-LIN TSAI, CLEMENT HSINGJEN WANN
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Publication number: 20240194794Abstract: Present disclosure provides a method including: forming a semiconductor stack having at least one SiGe layer; forming a plurality of fins from the semiconductor stack by a first etching operation, each of the plurality of fins comprising a first portion and a second portion over the first portion, the first portion being separated from the second portion by a SiGe portion; forming a poly gate stripe orthogonally over the plurality of fins; forming a recess on each of the plurality of fins abutting the poly gate; recessing the SiGe portion by a second etching operation through the recess; forming a first spacer and a second spacer to surround the SiGe portion; and removing the SiGe portion.Type: ApplicationFiled: January 18, 2024Publication date: June 13, 2024Inventors: CHIA-MING HSU, YI-JING LI, CHIH-HSIN KO, KUANG-HSIN CHEN, DA-WEN LIN, CLEMENT HSINGJEN WANN
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Publication number: 20240154028Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include a channel layer and a buffer layer between the channel layer and the substrate. The method can further include forming a recess structure in the channel layer. The recess structure can include a bottom surface over the buffer layer. The method can further include forming a first epitaxial layer over the bottom surface of the recess structure. The first epitaxial layer can include a first atomic concentration of germanium. The method can further include forming a second epitaxial layer over the first epitaxial layer. The second epitaxial layer can include a second atomic concentration of germanium greater than the first atomic concentration of germanium.Type: ApplicationFiled: January 17, 2024Publication date: May 9, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Heng LI, Yi-Jing LI, Chia-Der CHANG
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Patent number: 11942467Abstract: A semiconductor structure includes a first metal-dielectric-metal layer, a first dielectric layer, a first conductive layer, a second conductive layer, and a second dielectric layer. The first metal-dielectric-metal layer includes a plurality of first fingers, a plurality of second fingers, and a first dielectric material. The first fingers are electrically connected to a first voltage. The second fingers are electrically connected to a second voltage different from the first voltage, and the first fingers and the second fingers are arranged in parallel and staggeredly. The first dielectric material is between the first fingers and the second fingers. The first dielectric layer is over the first metal-dielectric-metal layer. The first conductive layer is over the first dielectric layer. The second conductive layer is over the first conductive layer. The second dielectric layer is between the first conductive layer and the second conductive layer.Type: GrantFiled: June 18, 2021Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: I-Sheng Chen, Yi-Jing Li, Chia-Ming Hsu, Wan-Lin Tsai, Clement Hsingjen Wann
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Patent number: 11923436Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include a channel layer and a buffer layer between the channel layer and the substrate. The method can further include forming a recess structure in the channel layer. The recess structure can include a bottom surface over the buffer layer. The method can further include forming a first epitaxial layer over the bottom surface of the recess structure. The first epitaxial layer can include a first atomic concentration of germanium. The method can further include forming a second epitaxial layer over the first epitaxial layer. The second epitaxial layer can include a second atomic concentration of germanium greater than the first atomic concentration of germanium.Type: GrantFiled: April 1, 2021Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chen-Heng Li, Yi-Jing Li, Chia-Der Chang
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Patent number: 11916151Abstract: Present disclosure provides a semiconductor structure, including a semiconductor fin having a first portion and a second portion over the first portion, a first conductive region abutting a first lateral surface of the first portion and a first lateral surface of the second portion, a metal gate having a bottom portion and an upper portion, the bottom portion being between the first portion and the second portion of the semiconductor fin, and the upper portion being over the second portion of the semiconductor fin, and a first spacer between the bottom portion of the metal gate and the first conductive region. A method for manufacturing the semiconductor structure described herein is also provided.Type: GrantFiled: June 25, 2021Date of Patent: February 27, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chia-Ming Hsu, Yi-Jing Li, Chih-Hsin Ko, Kuang-Hsin Chen, Da-Wen Lin, Clement Hsingjen Wann
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Publication number: 20230298944Abstract: The present disclosure describes a method that includes forming a fin protruding from a substrate, the fin including a first sidewall and a second sidewall formed opposite to the first sidewall. The method also includes depositing a shallow-trench isolation (STI) material on the substrate. Depositing the STI material includes depositing a first portion of the STI material in contact with the first sidewall and depositing a second portion of the STI material in contact with the second sidewall. The method also includes performing a first etching process on the STI material to etch the first portion of the STI material at a first etching rate and the second portion of the STI material at a second etching rate greater than the first etching rate. The method also includes performing a second etching process on the STI material to etch the first portion of the STI material at a third etching rate and the second portion of the STI material at a fourth etching rate less than the third etching rate.Type: ApplicationFiled: May 25, 2023Publication date: September 21, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: I-Sheng CHEN, Yi-Jing LI, Chen-Heng LI
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Patent number: 11699620Abstract: The present disclosure describes a method that includes forming a fin protruding from a substrate, the fin including a first sidewall and a second sidewall formed opposite to the first sidewall. The method also includes depositing a shallow-trench isolation (STI) material on the substrate. Depositing the STI material includes depositing a first portion of the STI material in contact with the first sidewall and depositing a second portion of the STI material in contact with the second sidewall. The method also includes performing a first etching process on the STI material to etch the first portion of the STI material at a first etching rate and the second portion of the STI material at a second etching rate greater than the first etching rate. The method also includes performing a second etching process on the STI material to etch the first portion of the STI material at a third etching rate and the second portion of the STI material at a fourth etching rate less than the third etching rate.Type: GrantFiled: April 8, 2021Date of Patent: July 11, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: I-Sheng Chen, Yi-Jing Li, Chen-Heng Li
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Patent number: 11562910Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. A sacrificial gate layer is removed to form a gate trench exposing a sacrificial dielectric layer. An ion implantation is performed to a portion of a substrate covered by the sacrificial dielectric layer in the gate trench. The sacrificial dielectric layer is removed to expose the substrate from the gate trench. An interfacial layer is formed over the substrate in the gate trench. A metal gate structure is formed over the interfacial layer in the gate trench.Type: GrantFiled: March 19, 2021Date of Patent: January 24, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: I-Sheng Chen, Siao-Jing Li, Yi-Jing Li
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Publication number: 20220416090Abstract: Present disclosure provides a semiconductor structure, including a semiconductor fin having a first portion and a second portion over the first portion, a first conductive region abutting a first lateral surface of the first portion and a first lateral surface of the second portion, a metal gate having a bottom portion and an upper portion, the bottom portion being between the first portion and the second portion of the semiconductor fin, and the upper portion being over the second portion of the semiconductor fin, and a first spacer between the bottom portion of the metal gate and the first conductive region. A method for manufacturing the semiconductor structure described herein is also provided.Type: ApplicationFiled: June 25, 2021Publication date: December 29, 2022Inventors: CHIA-MING HSU, YI-JING LI, CHIH-HSIN KO, KUANG-HSIN CHEN, DA-WEN LIN, CLEMENT HSINGJEN WANN
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Publication number: 20220406768Abstract: A semiconductor structure includes a first metal-dielectric-metal layer, a first dielectric layer, a first conductive layer, a second conductive layer, and a second dielectric layer. The first metal-dielectric-metal layer includes a plurality of first fingers, a plurality of second fingers, and a first dielectric material. The first fingers are electrically connected to a first voltage. The second fingers are electrically connected to a second voltage different from the first voltage, and the first fingers and the second fingers are arranged in parallel and staggeredly. The first dielectric material is between the first fingers and the second fingers. The first dielectric layer is over the first metal-dielectric-metal layer. The first conductive layer is over the first dielectric layer. The second conductive layer is over the first conductive layer. The second dielectric layer is between the first conductive layer and the second conductive layer.Type: ApplicationFiled: June 18, 2021Publication date: December 22, 2022Inventors: I-SHENG CHEN, YI-JING LI, CHIA-MING HSU, WAN-LIN TSAI, CLEMENT HSINGJEN WANN
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Publication number: 20220301885Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. A sacrificial gate layer is removed to form a gate trench exposing a sacrificial dielectric layer. An ion implantation is performed to a portion of a substrate covered by the sacrificial dielectric layer in the gate trench. The sacrificial dielectric layer is removed to expose the substrate from the gate trench. An interfacial layer is formed over the substrate in the gate trench. A metal gate structure is formed over the interfacial layer in the gate trench.Type: ApplicationFiled: March 19, 2021Publication date: September 22, 2022Inventors: I-SHENG CHEN, SIAO-JING LI, YI-JING LI
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Publication number: 20220045198Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include a channel layer and a buffer layer between the channel layer and the substrate. The method can further include forming a recess structure in the channel layer. The recess structure can include a bottom surface over the buffer layer. The method can further include forming a first epitaxial layer over the bottom surface of the recess structure. The first epitaxial layer can include a first atomic concentration of germanium. The method can further include forming a second epitaxial layer over the first epitaxial layer. The second epitaxial layer can include a second atomic concentration of germanium greater than the first atomic concentration of germanium.Type: ApplicationFiled: April 1, 2021Publication date: February 10, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chen-Heng LI, Yi-Jing Li, Chia-Der Chang
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Publication number: 20210375693Abstract: The present disclosure describes a method that includes forming a fin protruding from a substrate, the fin including a first sidewall and a second sidewall formed opposite to the first sidewall. The method also includes depositing a shallow-trench isolation (STI) material on the substrate. Depositing the STI material includes depositing a first portion of the STI material in contact with the first sidewall and depositing a second portion of the STI material in contact with the second sidewall. The method also includes performing a first etching process on the STI material to etch the first portion of the STI material at a first etching rate and the second portion of the STI material at a second etching rate greater than the first etching rate. The method also includes performing a second etching process on the STI material to etch the first portion of the STI material at a third etching rate and the second portion of the STI material at a fourth etching rate less than the third etching rate.Type: ApplicationFiled: April 8, 2021Publication date: December 2, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: I-Sheng CHEN, Yi-Jing LI, Chen-Heng LI
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Patent number: 9650266Abstract: A method of treating suspended solids and heavy metal ions in sewage includes (step 1) adding an iron sulfate reagent to a portion of sewage to be treated such that suspended solids therein undergo preliminary precipitation, and then separating the portion of sewage into primarily treated sewage with low turbidity and low density sludge (LDS); (step 2) filling a tank with the LDS, wherein the tank comprises a first inlet and a first outlet above the first inlet; and (step 3) conveying the other portion of sewage to be treated or the preliminarily treated sewage to the tank through the first inlet such that the sewage percolates though the LDS in the tank to fluidize the LDS and bind the suspended solid to the LDS, and in consequence, after percolating through the sludge, the treated sewage exits the tank through the outlet effluent.Type: GrantFiled: October 14, 2014Date of Patent: May 16, 2017Assignee: INSTITUTE OF NUCLEAR ENERGY RESEARCH, ATOMIC ENERGY COUNCIL, EXECUTIVE YUANInventors: Chun-Ping Huang, Yi-Jing Li, Yen-Nung Lai
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Publication number: 20160101999Abstract: A method of treating suspended solids and heavy metal ions in sewage includes (step 1) adding an iron sulfate reagent to a portion of sewage to be treated such that suspended solids therein undergo preliminary precipitation, and then separating the portion of sewage into primarily treated sewage with low turbidity and low density sludge (LDS); (step 2) filling a tank with the LDS, wherein the tank comprises a first inlet and a first outlet above the first inlet; and (step 3) conveying the other portion of sewage to be treated or the preliminarily treated sewage to the tank through the first inlet such that the sewage percolates though the LDS in the tank to fluidize the LDS and bind the suspended solid to the LDS, and in consequence, after percolating through the sludge, the treated sewage exits the tank through the outlet effluent.Type: ApplicationFiled: October 14, 2014Publication date: April 14, 2016Inventors: CHUN-PING HUANG, YI-JING LI, YEN-NUNG LAI