Patents by Inventor Yi-Jiun Lin

Yi-Jiun Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7030444
    Abstract: A split gate flash memory cell structure is disclosed for prevention of reverse tunneling. A gate insulator layer is formed over a semiconductor surface and a floating gate is disposed over the gate insulator layer. A floating gate insulator layer is disposed over the floating gate and sidewall insulator spacers are disposed along bottom portions of the floating gate sidewall adjacent to said gate insulator layer. The sidewall insulator spacers are formed from a spacer insulator layer that had been deposited in a manner that constitutes a minimal expenditure of an available thermal budget and etching processes used in fashioning the sidewall insulator spacers etch the spacer insulator layer faster than the gate insulator layer and the floating gate insulator layer. An intergate insulator layer is disposed over exposed portions of the gate insulator layer, the floating gate, the floating gate insulator layer and the sidewall insulator spacers.
    Type: Grant
    Filed: February 25, 2004
    Date of Patent: April 18, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Chi Tu, Wen-Ting Chu, Yi-Shing Chang, Yi-Jiun Lin
  • Publication number: 20050202631
    Abstract: A method for forming triple polysilicon split gate electrodes in a EEPROM flash memory array providing a first gate structure; blanket depositing a first polysilicon layer over the first gate structure; etching back the first polysilicon layer according to a first dry etching process; blanket depositing a second dielectric insulating layer over the first polysilicon layer; blanket depositing a second polysilicon layer over the second dielectric insulating layer; and, lithographically patterning and dry etching according to a respective third and fourth dry etching process through a thickness portion of the respective second and first polysilicon layers to respectively form third and second polysilicon gate electrodes.
    Type: Application
    Filed: October 15, 2003
    Publication date: September 15, 2005
    Inventors: Hsiang-Fan Lee, Shih-Wei Wang, Yi-Jiun Lin, Kuo-Wei Chu, Ching-Sen Kuo, Chia-Tong Ho
  • Publication number: 20050184331
    Abstract: A split gate flash memory cell structure is disclosed for prevention of reverse tunneling. A gate insulator layer is formed over a semiconductor surface and a floating gate is disposed over the gate insulator layer. A floating gate insulator layer is disposed over the floating gate and sidewall insulator spacers are disposed along bottom portions of the floating gate sidewall adjacent to said gate insulator layer. The sidewall insulator spacers are formed from a spacer insulator layer that had been deposited in a manner that constitutes a minimal expenditure of an available thermal budget and etching processes used in fashioning the sidewall insulator spacers etch the spacer insulator layer faster than the gate insulator layer and the floating gate insulator layer. An intergate insulator layer is disposed over exposed portions of the gate insulator layer, the floating gate, the floating gate insulator layer and the sidewall insulator spacers.
    Type: Application
    Filed: February 25, 2004
    Publication date: August 25, 2005
    Inventors: Kuo-Chi Tu, Wen-Ting Chu, Yi-Shing Chang, Yi-Jiun Lin
  • Publication number: 20050156224
    Abstract: A new method to form MOS gates in an integrated circuit device is achieved. The method is particularly useful for forming floating gates in split gate flash transistors. The method comprises providing a substrate. A dielectric layer is formed overlying the substrate. A conductor layer is formed overlying the dielectric layer. A first masking layer is deposited overlying the conductor layer. The first masking layer is patterned to selectively expose the conductor layer. A second masking layer is deposited overlying the first masking layer and the conductor layer. The second masking layer is etched back to form spacers on sidewalls of the first masking layer. The conductor layer is etched through where exposed by the first masking layer and the spacers to thereby form MOS gates in the manufacture of the integrated circuit device.
    Type: Application
    Filed: February 17, 2005
    Publication date: July 21, 2005
    Inventors: Chia-Ta Hsieh, Yi-Jiun Lin, Feng-Jia Shiu, Hung-Cheng Sung, Chi-Hsin Lo
  • Patent number: 6881629
    Abstract: A new method to form MOS gates in an integrated circuit device is achieved. The method is particularly useful for forming floating gates in split gate flash transistors. The method comprises providing a substrate. A dielectric layer is formed overlying the substrate. A conductor layer is formed overlying the dielectric layer. A first masking layer is deposited overlying the conductor layer. The first masking layer is patterned to selectively expose the conductor layer. A second masking layer is deposited overlying the first masking layer and the conductor layer. The second masking layer is etched back to form spacers on sidewalls of the first masking layer. The conductor layer is etched through where exposed by the first masking layer and the spacers to thereby form MOS gates in the manufacture of the integrated circuit device.
    Type: Grant
    Filed: September 5, 2003
    Date of Patent: April 19, 2005
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chia-Ta Hsieh, Yi-Jiun Lin, Feng-Jia Shiu, Hung-Cheng Sung, Chi-Hsin Lo
  • Publication number: 20050054162
    Abstract: A new method to form MOS gates in an integrated circuit device is achieved. The method is particularly useful for forming floating gates in split gate flash transistors. The method comprises providing a substrate. A dielectric layer is formed overlying the substrate. A conductor layer is formed overlying the dielectric layer. A first masking layer is deposited overlying the conductor layer. The first masking layer is patterned to selectively expose the conductor layer. A second masking layer is deposited overlying the first masking layer and the conductor layer. The second masking layer is etched back to form spacers on sidewalls of the first masking layer. The conductor layer is etched through where exposed by the first masking layer and the spacers to thereby form MOS gates in the manufacture of the integrated circuit device.
    Type: Application
    Filed: September 5, 2003
    Publication date: March 10, 2005
    Inventors: Chia-Ta Hsieh, Yi-Jiun Lin, Feng-Jia Shiu, Hung-Cheng Sung, Chi-Hsin Lo