Abstract: A method for host vibration test is disclosed in the present invention. The method includes outputting an initial power spectrum density to a testing platform by a data acquisition device so as to vibrate the testing platform according to the initial power spectrum density. A host is disposed on a supporter, and the supporter is set on the testing platform. The method further includes installing a first accelerometer on the supporter, generating a first power spectrum density according to data detected by the first accelerometer, installing a second accelerometer on the testing platform, generating a second power spectrum density according to data detected by the second accelerometer, and the data acquisition device executing the vibration test of a host according to the first power spectrum density and the second power spectrum density.

Abstract: A method for managing read/write (R/W) operations on an electronic device with hard disks, includes: upon receipt of R/W operation information related to an intended R/W operation, configuring a processor to decide which of the hard disks will be read/written with reference to the R/W operation information and sets of pre-established performance information. The sets respectively correspond to R/W operation settings. Each set includes multiple pieces of information each containing a performance indication related to a corresponding one of candidate combinations of the hard disks under the corresponding R/W operation setting. The decision is made with reference to the set, the R/W operation setting corresponding to which matches the R/W operation information.

Abstract: A hard disk device includes a hard disk having two opposite first sides, a second side interconnecting the first sides, and two corner portions defined by the first and second sides, and a slide rail mechanism including two first plates to be disposed slidably in a housing, and a second plate. Each first plate has a first section connected to the second plate, and a second section connected to the first section. The first section is spaced apart from the respective first side and is provided with a first support element for abutting against the corresponding corner portion. The second section abuts against the corresponding first side and is provided with positioning pins for engaging positioning holes in the corresponding first side. The second plate is spaced apart from the second side and is provided with second support elements for abutting against the second side.

Abstract: A fan control system includes a host device including a detecting unit for detecting a component so as to generate a detecting signal. The host device further includes BIOS for storing relationship information between the detecting signal and a rotational speed of a fan and for generating a rotational signal according to the detecting signal and the relationship information. The fan control system further includes a fan device including a fan and a fan driving unit for driving the fan. The fan device further includes a rotational speed modulating unit for controlling the fan driving unit to drive the fan to rotate at a second rotational speed outside a first range when a first rotational speed corresponding to the rotational signal according to the relationship information is within the first range.

Abstract: A heat dissipating device includes a supporting component installed on a circuit board. A plurality of openings is formed on the supporting component. The heat dissipating device further includes a plurality of heat dissipating components disposed on a side of the supporting component and installed inside the plurality of openings respectively for dissipating heat generated by a plurality of heat sources disposed on the other side of the supporting component. The heat dissipating device further includes a plurality of elastic components for pressing the plurality of heat dissipating components so that the plurality of heat dissipating components contacts the plurality of heat sources closely.

Abstract: A hard disk device includes a hard disk having two opposite first sides, a second side interconnecting the first sides, and two corner portions defined by the first and second sides, and a slide rail mechanism including two first plates to be disposed slidably in a housing, and a second plate. Each first plate has a first section connected to the second plate, and a second section connected to the first section. The first section is spaced apart from the respective first side and is provided with a first support element for abutting against the corresponding corner portion. The second section abuts against the corresponding first side and is provided with positioning pins for engaging positioning holes in the corresponding first side. The second plate is spaced apart from the second side and is provided with second support elements for abutting against the second side.

Abstract: A method for forming triple polysilicon split gate electrodes in a EEPROM flash memory array providing a first gate structure; blanket depositing a first polysilicon layer over the first gate structure; etching back the first polysilicon layer according to a first dry etching process; blanket depositing a second dielectric insulating layer over the first polysilicon layer; blanket depositing a second polysilicon layer over the second dielectric insulating layer; and, lithographically patterning and dry etching according to a respective third and fourth dry etching process through a thickness portion of the respective second and first polysilicon layers to respectively form third and second polysilicon gate electrodes.

Abstract: A split gate flash memory cell structure is disclosed for prevention of reverse tunneling. A gate insulator layer is formed over a semiconductor surface and a floating gate is disposed over the gate insulator layer. A floating gate insulator layer is disposed over the floating gate and sidewall insulator spacers are disposed along bottom portions of the floating gate sidewall adjacent to said gate insulator layer. The sidewall insulator spacers are formed from a spacer insulator layer that had been deposited in a manner that constitutes a minimal expenditure of an available thermal budget and etching processes used in fashioning the sidewall insulator spacers etch the spacer insulator layer faster than the gate insulator layer and the floating gate insulator layer. An intergate insulator layer is disposed over exposed portions of the gate insulator layer, the floating gate, the floating gate insulator layer and the sidewall insulator spacers.

Abstract: A method for forming triple polysilicon split gate electrodes in a EEPROM flash memory array providing a first gate structure; blanket depositing a first polysilicon layer over the first gate structure; etching back the first polysilicon layer according to a first dry etching process; blanket depositing a second dielectric insulating layer over the first polysilicon layer; blanket depositing a second polysilicon layer over the second dielectric insulating layer; and, lithographically patterning and dry etching according to a respective third and fourth dry etching process through a thickness portion of the respective second and first polysilicon layers to respectively form third and second polysilicon gate electrodes.

Abstract: A split gate flash memory cell structure is disclosed for prevention of reverse tunneling. A gate insulator layer is formed over a semiconductor surface and a floating gate is disposed over the gate insulator layer. A floating gate insulator layer is disposed over the floating gate and sidewall insulator spacers are disposed along bottom portions of the floating gate sidewall adjacent to said gate insulator layer. The sidewall insulator spacers are formed from a spacer insulator layer that had been deposited in a manner that constitutes a minimal expenditure of an available thermal budget and etching processes used in fashioning the sidewall insulator spacers etch the spacer insulator layer faster than the gate insulator layer and the floating gate insulator layer. An intergate insulator layer is disposed over exposed portions of the gate insulator layer, the floating gate, the floating gate insulator layer and the sidewall insulator spacers.

Abstract: A new method to form MOS gates in an integrated circuit device is achieved. The method is particularly useful for forming floating gates in split gate flash transistors. The method comprises providing a substrate. A dielectric layer is formed overlying the substrate. A conductor layer is formed overlying the dielectric layer. A first masking layer is deposited overlying the conductor layer. The first masking layer is patterned to selectively expose the conductor layer. A second masking layer is deposited overlying the first masking layer and the conductor layer. The second masking layer is etched back to form spacers on sidewalls of the first masking layer. The conductor layer is etched through where exposed by the first masking layer and the spacers to thereby form MOS gates in the manufacture of the integrated circuit device.

Abstract: A new method to form MOS gates in an integrated circuit device is achieved. The method is particularly useful for forming floating gates in split gate flash transistors. The method comprises providing a substrate. A dielectric layer is formed overlying the substrate. A conductor layer is formed overlying the dielectric layer. A first masking layer is deposited overlying the conductor layer. The first masking layer is patterned to selectively expose the conductor layer. A second masking layer is deposited overlying the first masking layer and the conductor layer. The second masking layer is etched back to form spacers on sidewalls of the first masking layer. The conductor layer is etched through where exposed by the first masking layer and the spacers to thereby form MOS gates in the manufacture of the integrated circuit device.

Abstract: A new method to form MOS gates in an integrated circuit device is achieved. The method is particularly useful for forming floating gates in split gate flash transistors. The method comprises providing a substrate. A dielectric layer is formed overlying the substrate. A conductor layer is formed overlying the dielectric layer. A first masking layer is deposited overlying the conductor layer. The first masking layer is patterned to selectively expose the conductor layer. A second masking layer is deposited overlying the first masking layer and the conductor layer. The second masking layer is etched back to form spacers on sidewalls of the first masking layer. The conductor layer is etched through where exposed by the first masking layer and the spacers to thereby form MOS gates in the manufacture of the integrated circuit device.