Abstract: A peripheral interface circuit and a peripheral memory system are provided. The peripheral interface circuit includes an interface sequencer, an input/output controller, a register unit and a data buffer. The interface sequencer receives requests from the input/output controller and accesses the peripheral memory in response to the requests. The data buffer is randomly accessed by address. If target data of the data access request exists in the data buffer, the input/output controller returns data from the data buffer in response to the request; if target data of the data access request does not exist in the data buffer, the input/output controller sends an interface request to the interface sequencer to access the peripheral memory and keeps a copy of at least the target data in the data buffer.

Abstract: A peripheral interface circuit and a peripheral memory system are provided. The peripheral interface circuit includes an interface sequencer, an input/output controller, a register unit and a data buffer. The interface sequencer receives requests from the input/output controller and accesses the peripheral memory in response to the requests. The data buffer is randomly accessed by address. If target data of the data access request exists in the data buffer, the input/output controller returns data from the data buffer in response to the request; if target data of the data access request does not exist in the data buffer, the input/output controller sends an interface request to the interface sequencer to access the peripheral memory and keeps a copy of at least the target data in the data buffer.

Abstract: An information collection system is provided. The information collection system includes an information collection unit, an information initiation unit, and an information relay unit. The information collection unit includes at least one slave port, and the information collection unit responds a transaction through the slave port. The information initiation unit includes at least one master port, and the information initiation unit initiates the transaction through the master port. The information relay unit includes at least one master port and at least one slave port, and the information relay unit relays the transaction through the master port and the slave port wherein the transaction includes a write transaction. Wherein, during an identification phase, the master port of the information initiation unit delivers a header, and the slave port of the information collection unit accepts the transaction according to the header.