Patents by Inventor Yi-Jou Lin
Yi-Jou Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240136546Abstract: A vacuum battery structural assembly and a vacuum multi-cell battery module composed thereof are provided and include a first repeating unit including a first frame plate and a second frame plate with respect to the first frame plate; and an electrolyte channel defined within the first frame plate and the second frame plate to accommodate a liquid electrolyte, wherein both a surface of the first frame plate and a surface of the second frame plate include a vacuum suction area, the vacuum suction area includes a vacuum aperture and a vacuum channel, wherein the vacuum aperture is formed on at least one surface of the first frame plate and the second frame plate, the vacuum channel is positioned inside the first frame plate and the second frame plate, and is configured to generate a longitudinal pressing suction force and seal the first frame plate and the second frame plate.Type: ApplicationFiled: November 23, 2022Publication date: April 25, 2024Inventors: Hung-Hsien Ku, Shang-Qing Zhuang, Ning-Yih Hsu, Chien-Hong Lin, Han-Jou Lin, Yi-Hsin Hu, Po-Yen Chiu, Yao-Ming Wang
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Publication number: 20240055358Abstract: An electronic package includes a base of a rectangular shape, and a chip package including a first interface circuit die and a second interface circuit die. The first interface circuit die and second interface circuit die are mounted on a redistribution layer structure and encapsulated within a molding compound. The chip package is mounted on a top surface of the base and rotated relative to the base above a vertical axis that is orthogonal to the top surface through a rotation offset angle. A metal ring is mounted on the top surface of the base.Type: ApplicationFiled: October 24, 2023Publication date: February 15, 2024Applicant: MEDIATEK INC.Inventors: Yao-Chun Su, Chih-Jung Hsu, Yi-Jou Lin, I-Hsuan Peng
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Publication number: 20240047427Abstract: A semiconductor package structure includes a substrate, a redistribution layer, a first semiconductor component, a conductive pillar, and a second semiconductor component. The redistribution layer is over the substrate. The first semiconductor component is over the redistribution layer. The conductive pillar is adjacent to the first semiconductor component, wherein the first semiconductor component and the conductive pillar are surrounded by a molding material. The second semiconductor component is over the molding material, wherein the second semiconductor component is electrically coupled to the redistribution layer through the conductive pillar.Type: ApplicationFiled: October 18, 2023Publication date: February 8, 2024Applicant: MediaTek Inc.Inventors: Yi-Lin Tsai, Wen-Sung Hsu, I-Hsuan Peng, Yi-Jou Lin
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Patent number: 11862578Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a substrate, a semiconductor die disposed over the substrate, and a frame disposed over the substrate. The frame is adjacent to the semiconductor die, and an upper surface of the frame is lower than the upper surface of the semiconductor die. IN addition, a passive component is disposed on the substrate and located between the frame and the semiconductor die.Type: GrantFiled: January 14, 2022Date of Patent: January 2, 2024Assignee: MEDIATEK INC.Inventors: Chia-Cheng Chang, Tzu-Hung Lin, I-Hsuan Peng, Yi-Jou Lin
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Patent number: 11854930Abstract: A semiconductor chip package includes a substrate having a top surface and a bottom surface, and a semiconductor device mounted on the top surface of the substrate. A gap is provided between the semiconductor device and the top surface of the substrate. A multi-layer laminate epoxy sheet is disposed on the top surface of the substrate and around a perimeter of the semiconductor device.Type: GrantFiled: September 1, 2022Date of Patent: December 26, 2023Assignee: MediaTek Inc.Inventors: Yi-Lin Tsai, Yi-Jou Lin, I-Hsuan Peng, Wen-Sung Hsu
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Patent number: 11830820Abstract: An electronic package includes a package substrate of a rectangular shape, and a chip package including a first interface circuit die and a second interface circuit die. The first interface circuit die and second interface circuit die are mounted on a redistribution layer structure and encapsulated within a molding compound. The chip package is mounted on a top surface of the package substrate and rotated relative to the package substrate above a vertical axis that is orthogonal to the top surface through a rotation offset angle. A metal ring is mounted on the top surface of the package substrate.Type: GrantFiled: December 16, 2021Date of Patent: November 28, 2023Assignee: MEDIATEK INC.Inventors: Yao-Chun Su, Chih-Jung Hsu, Yi-Jou Lin, I-Hsuan Peng
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Patent number: 11830851Abstract: A semiconductor package structure includes a substrate, a redistribution layer, a first semiconductor component, a conductive pillar, and a second semiconductor component. The redistribution layer is over the substrate. The first semiconductor component is over the redistribution layer. The conductive pillar is adjacent to the first semiconductor component, wherein the first semiconductor component and the conductive pillar are surrounded by a molding material. The second semiconductor component is over the molding material, wherein the second semiconductor component is electrically coupled to the redistribution layer through the conductive pillar.Type: GrantFiled: March 22, 2021Date of Patent: November 28, 2023Assignee: MediaTek Inc.Inventors: Yi-Lin Tsai, Wen-Sung Hsu, I-Hsuan Peng, Yi-Jou Lin
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Patent number: 11728232Abstract: A semiconductor package includes a package substrate having a top surface and a bottom surface, and a stiffener ring mounted on the top surface of the package substrate. The stiffener ring includes a reinforcement rib that is coplanar with the stiffener ring on the top surface of the package substrate. At least two compartments are defined by the stiffener ring and the reinforcement rib. At least two individual chip packages are mounted on chip mounting regions within the at least two compartments, respectively, thereby constituting a package array on the package substrate.Type: GrantFiled: March 2, 2022Date of Patent: August 15, 2023Assignee: MediaTek Inc.Inventors: Chi-Wen Pan, I-Hsuan Peng, Sheng-Liang Kuo, Yi-Jou Lin, Tai-Yu Chen
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Publication number: 20230197684Abstract: A semiconductor package structure includes a substrate having a substrate having a first surface and second surface opposite thereto, wherein the substrate comprises a wiring structure. The structure also has a first semiconductor die disposed on the first surface of the substrate and electrically coupled to the wiring structure, and a second semiconductor die disposed on the first surface and electrically coupled to the wiring structure, wherein the first semiconductor die and the second semiconductor die are arranged in a side-by-side manner. A molding material surrounds the first semiconductor die and the second semiconductor die, wherein the first semiconductor die is separated from the second semiconductor die by the molding material. Finally, an annular frame mounted on the first surface of the substrate, wherein the annular frame surrounds the first semiconductor die and the second semiconductor die.Type: ApplicationFiled: February 16, 2023Publication date: June 22, 2023Inventors: Chia-Cheng CHANG, Tzu-Hung LIN, I-Hsuan PENG, Yi-Jou LIN
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Patent number: 11670596Abstract: A semiconductor package structure includes a substrate, a first redistribution layer, a second redistribution layer, a bridge structure, a first semiconductor component, and a second semiconductor component. The first redistribution layer is over the substrate. The second redistribution layer is over the first redistribution layer. The bridge structure is between the first redistribution layer and the second redistribution layer, wherein the bridge structure includes an active device. The first semiconductor component and the second semiconductor component are located over the second redistribution layer, wherein the first semiconductor component is electrically coupled to the second semiconductor component through the second redistribution layer and the bridge structure.Type: GrantFiled: March 22, 2021Date of Patent: June 6, 2023Assignee: MEDIATEK INC.Inventors: Yi-Lin Tsai, Wen-Sung Hsu, I-Hsuan Peng, Yi-Jou Lin
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Patent number: 11646295Abstract: A semiconductor package structure includes a substrate having a substrate having a first surface and second surface opposite thereto, wherein the substrate comprises a wiring structure. The structure also has a first semiconductor die disposed on the first surface of the substrate and electrically coupled to the wiring structure, and a second semiconductor die disposed on the first surface and electrically coupled to the wiring structure, wherein the first semiconductor die and the second semiconductor die are arranged in a side-by-side manner. A molding material surrounds the first semiconductor die and the second semiconductor die, wherein the first semiconductor die is separated from the second semiconductor die by the molding material. Finally, an annular frame mounted on the first surface of the substrate, wherein the annular frame surrounds the first semiconductor die and the second semiconductor die.Type: GrantFiled: September 29, 2021Date of Patent: May 9, 2023Assignee: MEDIATEK INC.Inventors: Chia-Cheng Chang, Tzu-Hung Lin, I-Hsuan Peng, Yi-Jou Lin
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Publication number: 20230060065Abstract: A semiconductor package includes a substrate having a top surface and a bottom surface; a semiconductor die mounted on the top surface of the substrate; and a two-part lid mounted on a perimeter of the top surface of the substrate and housing the semiconductor die. The two-part lid comprises an annular lid base and a cover plate removably installed on the annular lid base.Type: ApplicationFiled: July 25, 2022Publication date: February 23, 2023Applicant: MEDIATEK INC.Inventors: Yi-Lin Tsai, Yi-Jou Lin, Tsai-Ming Lai, Wei-Chen Chang
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Publication number: 20230044797Abstract: A semiconductor package including at least one functional die; at least one dummy die free of active circuit, wherein the dummy die comprises at least one metal-insulator-metal (MIM) capacitor; and a redistribution layer (RDL) structure interconnecting the MIM capacitor to the at least one functional die.Type: ApplicationFiled: October 25, 2022Publication date: February 9, 2023Applicant: MediaTek Inc.Inventors: Yao-Chun Su, Chih-Ching Chen, I-Hsuan Peng, Yi-Jou Lin
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Publication number: 20230005808Abstract: A semiconductor chip package includes a substrate having a top surface and a bottom surface, and a semiconductor device mounted on the top surface of the substrate. A gap is provided between the semiconductor device and the top surface of the substrate. A multi-layer laminate epoxy sheet is disposed on the top surface of the substrate and around a perimeter of the semiconductor device.Type: ApplicationFiled: September 1, 2022Publication date: January 5, 2023Applicant: MEDIATEK INC.Inventors: Yi-Lin Tsai, Yi-Jou Lin, I-Hsuan Peng, Wen-Sung Hsu
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Patent number: 11508707Abstract: A semiconductor package including at least one functional die; at least one dummy die free of active circuit, wherein the dummy die comprises at least one metal-insulator-metal (MIM) capacitor; and a redistribution layer (RDL) structure interconnecting the MIM capacitor to the at least one functional die.Type: GrantFiled: May 7, 2020Date of Patent: November 22, 2022Assignee: MediaTek Inc.Inventors: Yao-Chun Su, Chih-Ching Chen, I-Hsuan Peng, Yi-Jou Lin
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Patent number: 11469152Abstract: A semiconductor chip package includes a substrate having a top surface and a bottom surface, and a semiconductor device mounted on the top surface of the substrate. A gap is provided between the semiconductor device and the top surface of the substrate. A pre-cut laminate epoxy sheet is disposed on the top surface of the substrate and around a perimeter of the semiconductor device.Type: GrantFiled: September 29, 2020Date of Patent: October 11, 2022Assignee: MEDIATEK INC.Inventors: Yi-Lin Tsai, Yi-Jou Lin, I-Hsuan Peng, Wen-Sung Hsu
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Publication number: 20220262691Abstract: A semiconductor package includes a package substrate having a top surface and a bottom surface, and a stiffener ring mounted on the top surface of the package substrate. The stiffener ring includes a reinforcement rib that is coplanar with the stiffener ring on the top surface of the package substrate. At least two compartments are defined by the stiffener ring and the reinforcement rib. At least two individual chip packages are mounted on chip mounting regions within the at least two compartments, respectively, thereby constituting a package array on the package substrate.Type: ApplicationFiled: March 2, 2022Publication date: August 18, 2022Applicant: Media Tek Inc.Inventors: Chi-Wen Pan, I-Hsuan Peng, Sheng-Liang Kuo, Yi-Jou Lin, Tai-Yu Chen
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Publication number: 20220238446Abstract: A semiconductor package structure includes a first semiconductor die and a second semiconductor die neighboring the first semiconductor die. The first semiconductor die includes a first edge, a second edge opposite the first edge, and a first metal layer exposed from the second edge. The second semiconductor includes a third edge neighboring the second edge of the first semiconductor die, a fourth edge opposite the third edge, and a second metal layer exposed from the third edge. The first metal layer of the first semiconductor die is electrically connected to the second metal layer of the second semiconductor die.Type: ApplicationFiled: April 12, 2022Publication date: July 28, 2022Applicant: MediaTek Inc.Inventors: Po-Hao CHANG, Yi-Jou Lin, Hung-Chuan Chen
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Patent number: 11342267Abstract: A semiconductor package structure includes a first semiconductor die and a second semiconductor die neighboring the first semiconductor die. The first semiconductor die includes a first edge, a second edge opposite the first edge, and a first metal layer exposed from the second edge. The second semiconductor includes a third edge neighboring the second edge of the first semiconductor die, a fourth edge opposite the third edge, and a second metal layer exposed from the third edge. The first metal layer of the first semiconductor die is electrically connected to the second metal layer of the second semiconductor die.Type: GrantFiled: October 23, 2019Date of Patent: May 24, 2022Assignee: MediaTek Inc.Inventors: Po-Hao Chang, Yi-Jou Lin, Hung-Chuan Chen
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Publication number: 20220139848Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a substrate, a semiconductor die disposed over the substrate, and a frame disposed over the substrate. The frame is adjacent to the semiconductor die, and an upper surface of the frame is lower than the upper surface of the semiconductor die. IN addition, a passive component is disposed on the substrate and located between the frame and the semiconductor die.Type: ApplicationFiled: January 14, 2022Publication date: May 5, 2022Inventors: Chia-Cheng CHANG, Tzu-Hung LIN, I-Hsuan PENG, Yi-Jou LIN