Patents by Inventor Yi-Jung Chen

Yi-Jung Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240387265
    Abstract: A method includes forming a dielectric layer over an epitaxial source/drain region. An opening is formed in the dielectric layer. The opening exposes a portion of the epitaxial source/drain region. A barrier layer is formed on a sidewall and a bottom of the opening. An oxidation process is performing on the sidewall and the bottom of the opening. The oxidation process transforms a portion of the barrier layer into an oxidized barrier layer and transforms a portion of the dielectric layer adjacent to the oxidized barrier layer into a liner layer. The oxidized barrier layer is removed. The opening is filled with a conductive material in a bottom-up manner. The conductive material is in physical contact with the liner layer.
    Type: Application
    Filed: July 28, 2024
    Publication date: November 21, 2024
    Inventors: Pin-Wen Chen, Chang-Ting Chung, Yi-Hsiang Chao, Yu-Ting Wen, Kai-Chieh Yang, Yu-Chen Ko, Peng-Hao Hsu, Ya-Yi Cheng, Min-Hsiu Hung, Chun-Hsien Huang, Wei-Jung Lin, Chih-Wei Chang, Ming-Hsing Tsai
  • Publication number: 20240387206
    Abstract: A pickup apparatus for separating a semiconductor die adhered on an adhesive film therefrom includes a frame, an UV light emitting element, and a collector element. The frame is configurated to hold the adhesive film adhered with the semiconductor die thereon. The UV light emitting element is disposed inside the frame, where the adhesive film is disposed between the semiconductor die and the UV light emitting element. The collector element is disposed over the frame.
    Type: Application
    Filed: July 26, 2024
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jung Chen, Tsung-Fu Tsai, Szu-Wei Lu
  • Publication number: 20240387418
    Abstract: A semiconductor device includes a bottom wafer, a top wafer bonded to the bottom wafer, a first dielectric layer, a second dielectric layer, a deep via conductor structure, and a connection pad. The top wafer includes a first interconnection structure. The first dielectric layer is disposed on the top wafer. The second dielectric layer is disposed on the first dielectric layer. The deep via conductor structure penetrates through the second dielectric layer and the first dielectric layer and is connected with the first interconnection structure. The connection pad is disposed on the second dielectric layer and the deep via conductor structure. A first portion of the second dielectric layer is sandwiched between the connection pad and the first dielectric layer. A second portion of the second dielectric layer is connected with the first portion, and a thickness of the second portion is less than a thickness of the first portion.
    Type: Application
    Filed: June 14, 2023
    Publication date: November 21, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Chun Chen, Yu-Ping Wang, I-Ming Tseng, Yi-An Shih, Chung-Sung Chiang, Chiu-Jung Chiu
  • Patent number: 12142499
    Abstract: A pickup apparatus for separating a semiconductor die adhered on an adhesive film therefrom includes a frame, an UV light emitting element, and a collector element. The frame is configurated to hold the adhesive film adhered with the semiconductor die thereon. The UV light emitting element is disposed inside the frame, where the adhesive film is disposed between the semiconductor die and the UV light emitting element. The collector element is disposed over the frame.
    Type: Grant
    Filed: January 17, 2022
    Date of Patent: November 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jung Chen, Tsung-Fu Tsai, Szu-Wei Lu
  • Publication number: 20240371758
    Abstract: A method for fabricating a semiconductor device includes the steps of first bonding a top wafer to a bottom wafer, in which the top wafer has a first metal interconnection including a first barrier layer exposing from a bottom surface of the top wafer. Next, a dielectric layer is formed on the bottom surface of the top wafer and then a second metal interconnection is formed in the dielectric layer and connected to the first metal interconnection, in which the second metal interconnection includes a second barrier layer and the first barrier layer and the second barrier layer include a H-shape altogether.
    Type: Application
    Filed: May 31, 2023
    Publication date: November 7, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Chun Chen, Yu-Ping Wang, I-Ming Tseng, Yi-An Shih, Chung-Sung Chiang, Chiu-Jung Chiu
  • Publication number: 20240357943
    Abstract: A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a trench in the IMD layer, forming a synthetic antiferromagnetic (SAF) layer in the trench, forming a metal layer on the SAF layer, planarizing the metal layer and the SAF layer to form a metal interconnection, and forming a magnetic tunneling junction (MTJ) on the metal interconnection.
    Type: Application
    Filed: June 30, 2024
    Publication date: October 24, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chiu-Jung Chiu, Ya-Sheng Feng, I-Ming Tseng, Yi-An Shih, Yu-Chun Chen, Yi-Hui Lee, Chung-Liang Chu, Hsiu-Hao Hu
  • Publication number: 20240339774
    Abstract: A board end connector includes a cage. The cage surrounds a accommodating space. The cage has at least one elastic bridge and at least one alignment hole. The elastic bridge is located on a surface of the cage and recessed toward the accommodating space. When the elastic bridge is abutted against an external component, the elastic bridge is elastically deformed and applies a reverse force to the external component, thereby changing the position of a portion of the external component in the alignment hole.
    Type: Application
    Filed: April 3, 2024
    Publication date: October 10, 2024
    Inventors: Yi-Hsing CHUNG, Shi-Jung CHEN
  • Patent number: 12108131
    Abstract: An assembling method for an optical system is provided, including: providing a first movable portion, connecting the first movable portion to a first fixed portion, providing a second movable portion, connecting the second movable portion to a second fixed portion, engaging the first fixed portion to the second fixed portion, adjusting the position of the first movable portion relative to the first fixed portion to a first predetermined position and temporarily affixing the first movable portion in the first predetermined position, affixing a first optical member to the first movable portion, and affixing a second optical member to the second movable portion.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: October 1, 2024
    Assignee: TDK TAIWAN CORP.
    Inventors: Shao-Chung Chang, Chan-Jung Hsu, Yi-Ho Chen
  • Patent number: 12096023
    Abstract: A video coder may determine a motion vector of a non-adjacent block of a current picture of the video data. The non-adjacent block is non-adjacent to a current block of the current picture. Furthermore, the video coder determines, based on the motion vector of the non-adjacent block, a motion vector predictor (MVP) for the current block. The video coder may determine a motion vector of the current block. The video coder may also determine a predictive block based on the motion vector of the current block.
    Type: Grant
    Filed: May 5, 2023
    Date of Patent: September 17, 2024
    Assignee: QUALCOMM INCORPORATED
    Inventors: Yi-Wen Chen, Wei-Jung Chien, Yu-Chen Sun, Li Zhang, Sungwon Lee, Xiang Li, Hsiao-Chiang Chuang, Jianle Chen, Vadim Seregin, Marta Karczewicz
  • Patent number: 12063871
    Abstract: A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a trench in the IMD layer, forming a synthetic antiferromagnetic (SAF) layer in the trench, forming a metal layer on the SAF layer, planarizing the metal layer and the SAF layer to form a metal interconnection, and forming a magnetic tunneling junction (MTJ) on the metal interconnection.
    Type: Grant
    Filed: August 4, 2023
    Date of Patent: August 13, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chiu-Jung Chiu, Ya-Sheng Feng, I-Ming Tseng, Yi-An Shih, Yu-Chun Chen, Yi-Hui Lee, Chung-Liang Chu, Hsiu-Hao Hu
  • Patent number: 12050546
    Abstract: Disclosed is a data processing device including a main SoC, a performance-enhancing SoC, and an external circuit that is set outside any of the two SoCs. The main SoC includes: a first central processing unit (CPU) dividing to-be-processed data into a first input part and a second input part, and processing the first input part to generate first output data; and a first transceiver circuit forwarding the second input part to the performance-enhancing SoC via the external circuit, and then receiving second output data via the external circuit and forwarding it. The performance-enhancing SoC includes: a second transceiver circuit receiving the second input part via the external circuit, and transmitting the second output data to the main SoC via the external circuit; and a second CPU receiving the second input part from the second transceiver circuit and processing it to provide the second output data for the second transceiver circuit.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: July 30, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Yi-Cheng Chen, Hsu-Jung Tung
  • Patent number: 11983052
    Abstract: A display device and a bezel thereof are provided. The display device includes a display panel and a bezel. The display panel has a first surface and a second surface. The first surface includes at least one pixel pad section, and the second surface includes at least one circuit pad section. The bezel includes a first surface connecting portion, a second surface connecting portion and at least one conductive wire. The edge of the display panel having the pixel pad section and the circuit pad section is accommodated between the first surface connecting portion and the second surface connecting portion. Each conductive wire has a first end and a second end. The first end is disposed on the first surface connecting portion and the second end is disposed on the second surface connecting portion. The part of the first connecting portion having the first end corresponds to the pixel pad section, and the part of the second connecting portion having the second end corresponds to the circuit pad section.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: May 14, 2024
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Yi-Fan Chen, Che-Chia Chang, Shang-Jie Wu, Yu-Chieh Kuo, Yi-Jung Chen, Yu-Hsun Chiu, Mei-Yi Li, He-Yi Cheng
  • Publication number: 20240128217
    Abstract: A semiconductor device includes a first semiconductor die and a second semiconductor die connected to the first semiconductor die. Each of the first semiconductor die and the second semiconductor die includes a substrate, a conductive bump formed on the substrate and a conductive contact formed on the conductive bump. The conductive contact has an outer lateral sidewall, there is an inner acute angle included between the outer lateral sidewall and the substrate is smaller than 85°, and the conductive contact of the first semiconductor die is connected opposite to the conductive contact of the second semiconductor die.
    Type: Application
    Filed: January 20, 2023
    Publication date: April 18, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jung CHEN, Chen Chiang YU, Wei-An TSAO, Tsung-Fu TSAI, Szu-Wei LU, Chung-Shi LIU
  • Publication number: 20240071982
    Abstract: In an embodiment, a device bonding apparatus is provided. The device bonding apparatus includes a first process station configured to receive a wafer; a first bond head configured to carry a die to the wafer, wherein the first bonding head includes a first rigid body and a vacuum channel in the first rigid body for providing an attaching force for carrying the die to the wafer; and a second bond head configured to press the die against the wafer, the second bond head including a second rigid body and an elastic head disposed over the second rigid body for pressing the die, the elastic head having a center portion and an edge portion surrounding the center portion, the center portion of the elastic head having a first thickness, the edge portion of the elastic head having a second thickness, the second thickness being greater than the second thickness.
    Type: Application
    Filed: August 25, 2022
    Publication date: February 29, 2024
    Inventors: Yi-Jung Chen, Tsung-Fu Tsai, Szu-Wei Lu
  • Publication number: 20240063043
    Abstract: A method for forming a semiconductor device is provided. The method includes providing a wafer with multiple semiconductor dies on the adhesive film held by the frame element. The method also includes lifting a semiconductor die up from the wafer using an ejector element. The method includes picking up the semiconductor die with a collector element. The method further includes flip-chipping the semiconductor die with the collector element, and picking up the semiconductor die from the collector element using a bond-head element. In addition, the method includes measuring the warpage of the semiconductor die on the bond-head element using a sensor, then bonding the semiconductor die to a carrier using the bond-head element.
    Type: Application
    Filed: August 16, 2022
    Publication date: February 22, 2024
    Inventors: Yi-Jung CHEN, Tsung-Fu TSAI, Szu-Wei LU, Chung-Shi LIU
  • Publication number: 20240063204
    Abstract: Integrated circuit package structures and methods of forming integrated circuit package structures are discussed. An integrated circuit package structure, in accordance with some embodiments, includes an integrated circuit package substrate with a heterogeneous bonding scheme that includes conductive pillars for bonding semiconductor devices to as well as a region including conductive connectors embedded in a dielectric for bonding additional semiconductor devices.
    Type: Application
    Filed: August 22, 2022
    Publication date: February 22, 2024
    Inventors: Yi-Jung Chen, Tsung-Fu Tsai, Szu-Wei Lu, Chung-Shi Liu
  • Publication number: 20230419883
    Abstract: A display device includes a multiple of light-emitting elements and a multiple of driving circuits. Each of the multiple of driving circuits is configured to generate a driving current flowing through one of the multiple of light-emitting elements. Each of the multiple of driving circuits includes a first transistor, a second transistor, a reset circuit, a first control circuit and a second control circuit. The driving current flows from a first system high voltage terminal through the first transistor, the second transistor and one of the multiple of light-emitting elements to a system low voltage terminal. The first control circuit is configured to control the first transistor to modulate pulse amplitude of the driving current. The second control circuit is configured to control the second transistor to modulate pulse width of the driving current.
    Type: Application
    Filed: September 7, 2023
    Publication date: December 28, 2023
    Inventors: Che-Chia CHANG, Shang-Jie WU, Yu-Chieh KUO, Hsien-Chun WANG, Sin-An LIN, Mei-Yi LI, Yu-Hsun CHIU, Ming-Hung CHUANG, Yi-Jung CHEN
  • Publication number: 20230369370
    Abstract: A package structure includes an optical die, an optical die, a supporting structure, and a lens structure. The optical die includes a photonic region. The optical die is disposed on and electrically coupled to the optical die. The supporting structure is disposed on the optical die, where the electric die is disposed between the supporting structure and the optical die. The lens structure is disposed on the supporting structure and optically coupled to the photonic region of the optical die, where the supporting structure is disposed between the lens structure and the electric die.
    Type: Application
    Filed: May 13, 2022
    Publication date: November 16, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jung Chen, Tsung-Fu Tsai, Szu-Wei Lu, Wei-An Tsao, Che-Yuan Yang, Chien-Ting Chen, Chih-Chieh Hung
  • Publication number: 20230343743
    Abstract: A flip-chip bonding method includes following operations. A wafer is provided with multiple semiconductor dies on an adhesive film held by a frame element. A semiconductor die is lifted up from the wafer by an ejector element. The semiconductor die is picked up with a collector element. The semiconductor die is flip-chipped with the collector element. An alignment check is performed to determine a position of the semiconductor die, so as to determine a process tolerance between a center of the collector element and a center of the semiconductor die. The semiconductor die with the collector element is transferred to a location underneath a bonder element based on the process tolerance of the alignment check. The semiconductor die is picked up from the collector element by the bonder element. The semiconductor die is bonded to a carrier by the bonder element.
    Type: Application
    Filed: April 21, 2022
    Publication date: October 26, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jung Chen, Tsung-Fu Tsai, Szu-Wei Lu
  • Patent number: 11790832
    Abstract: A display device includes a multiple of light-emitting elements and a multiple of driving circuits. Each of the multiple of driving circuits is configured to generate a driving current to illuminate one of the multiple of light-emitting elements. Each of the multiple of driving circuits includes a first transistor, a second transistor, a reset circuit, a first control circuit and a second control circuit. The driving current flows from a first system high voltage terminal through the first transistor, the second transistor and one of the multiple of light-emitting elements to a system low voltage terminal. The first control circuit is configured to control the first transistor to modulate pulse amplitude of the driving current. The second control circuit is configured to control the second transistor to modulate pulse width of the driving current.
    Type: Grant
    Filed: September 8, 2021
    Date of Patent: October 17, 2023
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Che-Chia Chang, Shang-Jie Wu, Yu-Chieh Kuo, Hsien-Chun Wang, Sin-An Lin, Mei-Yi Li, Yu-Hsun Chiu, Ming-Hung Chuang, Yi-Jung Chen