Patents by Inventor Yi-Jung Liu

Yi-Jung Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240145398
    Abstract: A carrier structure is provided, in which at least one positioning area is defined on a chip-placement area of a package substrate, and at least one alignment portion is disposed on the positioning area. Therefore, the precision of manufacturing the alignment portion is improved by disposing the positioning area on the chip-placement area, such that the carrier structure can provide a better alignment mechanism for the chip placement operation.
    Type: Application
    Filed: December 8, 2022
    Publication date: May 2, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Cheng-Liang HSU, Wan-Rou CHEN, Hsin-Yin CHANG, Tsung-Li LIN, Hsiu-Jung LI, Chiu-Lien LI, Fu-Quan XU, Yi-Wen LIU, Chih-Chieh SUN
  • Publication number: 20240133918
    Abstract: In a method for obtaining the equivalent oxide thickness of a dielectric layer, a first semiconductor capacitor including a first silicon dioxide layer and a second semiconductor capacitor including a second silicon dioxide layer are provided and a modulation voltage is applied to the semiconductor capacitors to measure a first scanning capacitance microscopic signal and a second scanning capacitance microscopic signal. According to the equivalent oxide thicknesses of the silicon dioxide layers and the scanning capacitance microscopic signals, an impedance ratio is calculated. The modulation voltage is applied to a third semiconductor capacitor including a dielectric layer to measure a third scanning capacitance microscopic signal. Finally, the equivalent oxide thickness of the dielectric layer is obtained according to the equivalent oxide thickness of the first silicon dioxide layer, the first scanning capacitance microscopic signal, third scanning capacitance microscopic signal, and the impedance ratio.
    Type: Application
    Filed: April 12, 2023
    Publication date: April 25, 2024
    Inventors: MAO-NAN CHANG, CHI-LUN LIU, HSUEH-LIANG CHOU, YI-SHAN WU, CHIAO-JUNG LIN, YU-HSUN HSUEH
  • Publication number: 20240136346
    Abstract: A semiconductor die package includes an inductor-capacitor (LC) semiconductor die that is directly bonded with a logic semiconductor die. The LC semiconductor die includes inductors and capacitors that are integrated into a single die. The inductors and capacitors of the LC semiconductor die may be electrically connected with transistors and other logic components on the logic semiconductor die to form a voltage regulator circuit of the semiconductor die package. The integration of passive components (e.g., the inductors and capacitors) of the voltage regulator circuit into a single semiconductor die reduces signal propagation distances in the voltage regulator circuit, which may increase the operating efficiency of the voltage regulator circuit, may reduce the formfactor for the semiconductor die package, may reduce parasitic capacitance and/or may reduce parasitic inductance in the voltage regulator circuit (thereby improving the performance of the voltage regulator circuit), among other examples.
    Type: Application
    Filed: April 17, 2023
    Publication date: April 25, 2024
    Inventors: Chien Hung LIU, Yu-Sheng CHEN, Yi Ching ONG, Hsien Jung CHEN, Kuen-Yi CHEN, Kuo-Ching HUANG, Harry-HakLay CHUANG, Wei-Cheng WU, Yu-Jen WANG
  • Publication number: 20240128217
    Abstract: A semiconductor device includes a first semiconductor die and a second semiconductor die connected to the first semiconductor die. Each of the first semiconductor die and the second semiconductor die includes a substrate, a conductive bump formed on the substrate and a conductive contact formed on the conductive bump. The conductive contact has an outer lateral sidewall, there is an inner acute angle included between the outer lateral sidewall and the substrate is smaller than 85°, and the conductive contact of the first semiconductor die is connected opposite to the conductive contact of the second semiconductor die.
    Type: Application
    Filed: January 20, 2023
    Publication date: April 18, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jung CHEN, Chen Chiang YU, Wei-An TSAO, Tsung-Fu TSAI, Szu-Wei LU, Chung-Shi LIU
  • Patent number: 11951571
    Abstract: A method of forming a package structure includes an etching step, a laser step, a plating step and a singulation step. In the etching step, a plurality of cutting streets of a leadframe are etched. In the laser step, a plastic package material covering on each of the cutting streets is removed via a laser beam. In the plating step, a plurality of plating surfaces are disposed on a plurality of areas of the leadframe without the plastic package material. In the singulation step, the cutting streets of the leadframe are cut to form the package structure.
    Type: Grant
    Filed: February 2, 2023
    Date of Patent: April 9, 2024
    Assignee: INTEGRATED SILICON SOLUTION INC.
    Inventors: Cheng-Fu Yu, Kai-Jih Shih, Yi-Jung Liu
  • Publication number: 20230275804
    Abstract: This disclosure provides a method for establishing a network connection between an intelligent baseboard management controller and a management server. The intelligent baseboard management controller is disposed on a motherboard of an electronic device. A connection configuration program is installed in the electronic device, and the electronic device executes the connection configuration program to transmit a connection information packet to the intelligent baseboard management controller. After receiving the connection information packet, the intelligent baseboard management controller parses a connection information of the management server from the connection information packet, and executes a network connection procedure according to the connection information of the management server, so that the network connection between the intelligent baseboard management controller and the management server is established.
    Type: Application
    Filed: May 27, 2022
    Publication date: August 31, 2023
    Inventors: Shu-ming Chang, Shang-Ju Lin, Yi-Jung Liu
  • Publication number: 20230173615
    Abstract: A method of forming a package structure includes an etching step, a laser step, a plating step and a singulation step. In the etching step, a plurality of cutting streets of a leadframe are etched. In the laser step, a plastic package material covering on each of the cutting streets is removed via a laser beam. In the plating step, a plurality of plating surfaces are disposed on a plurality of areas of the leadframe without the plastic package material. In the singulation step, the cutting streets of the leadframe are cut to form the package structure.
    Type: Application
    Filed: February 2, 2023
    Publication date: June 8, 2023
    Inventors: Cheng-Fu YU, Kai-Jih SHIH, Yi-Jung LIU
  • Patent number: 11612965
    Abstract: A method of forming a package structure includes an etching step, a laser step, a plating step and a singulation step. In the etching step, a plurality of cutting streets of a leadframe are etched. In the laser step, a plastic package material covering on each of the cutting streets is removed via a laser beam. In the plating step, a plurality of plating surfaces are disposed on a plurality of areas of the leadframe without the plastic package material. In the singulation step, the cutting streets of the leadframe are cut to form the package structure.
    Type: Grant
    Filed: December 2, 2020
    Date of Patent: March 28, 2023
    Assignee: INTEGRATED SILICON SOLUTION INC.
    Inventors: Cheng-Fu Yu, Kai-Jih Shih, Yi-Jung Liu
  • Publication number: 20210305136
    Abstract: A package structure includes a leadframe, a semiconductor die and a plastic package material. The leadframe includes a die pad and a plurality of leads. The leads are disposed on four sides of the die pad, and each of the leads includes a plurality of plating surfaces. The semiconductor die is disposed on the die pad of the leadframe. The plastic package material is disposed on the leadframe. Each of the leads protrudes an outer region of the plastic package material.
    Type: Application
    Filed: December 2, 2020
    Publication date: September 30, 2021
    Inventors: Cheng-Fu YU, Kai-Jih SHIH, Yi-Jung LIU, Chi-Yi Wu
  • Publication number: 20210299791
    Abstract: A method of forming a package structure includes an etching step, a laser step, a plating step and a singulation step. In the etching step, a plurality of cutting streets of a leadframe are etched. In the laser step, a plastic package material covering on each of the cutting streets is removed via a laser beam. In the plating step, a plurality of plating surfaces are disposed on a plurality of areas of the leadframe without the plastic package material. In the singulation step, the cutting streets of the leadframe are cut to form the package structure.
    Type: Application
    Filed: December 2, 2020
    Publication date: September 30, 2021
    Inventors: Cheng-Fu YU, Kai-Jih SHIH, Yi-Jung LIU
  • Patent number: 9748175
    Abstract: A method for manufacturing a semiconductor structure is provided. The method for manufacturing a semiconductor structure includes forming an organosilicon layer over a substrate and etching the organosilicon layer to have a trench. The method for manufacturing a semiconductor structure further includes forming a conductive structure in the trench. In addition, the organosilicon layer is made of a material including Si—C bonding and Si—O bonding, and a ratio of an amount of the Si—C bonding to an amount of the Si—O bonding is greater than about 0.2.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: August 29, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Jung Liu, Huan-Wei Wu, Chester Tang, Joung-Wei Liou
  • Patent number: 9282631
    Abstract: Circuit with flat electromagnetic band gap resonance structure, includes a plurality of flat units formed at a conductor layer; each flat unit spirally revolves inward from a first end to an internal point following a rotation direction, and spirally revolves outward from the internal point to a second end following an opposite rotation direction. Each flat unit is connected to a ground plane by a conductive stand (e.g., a via) at a connection point, for suppressing noise resonances at certain frequencies, and the frequencies are related to a stub length of each flat unit, and the stub length is related to a route length from the connection point to an end.
    Type: Grant
    Filed: August 5, 2014
    Date of Patent: March 8, 2016
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Wei Chiu, Yi-Jung Liu, Ling-Chih Chou
  • Publication number: 20150041185
    Abstract: Circuit with flat electromagnetic band gap resonance structure, includes a plurality of flat units formed at a conductor layer; each flat unit spirally revolves inward from a first end to an internal point following a rotation direction, and spirally revolves outward from the internal point to a second end following an opposite rotation direction. Each flat unit is connected to a ground plane by a conductive stand (e.g., a via) at a connection point, for suppressing noise resonances at certain frequencies, and the frequencies are related to a stub length of each flat unit, and the stub length is related to a route length from the connection point to an end.
    Type: Application
    Filed: August 5, 2014
    Publication date: February 12, 2015
    Inventors: Po-Wei Chiu, Yi-Jung Liu, Ling-Chih Chou