Patents by Inventor Yi-Jung Liu

Yi-Jung Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11951571
    Abstract: A method of forming a package structure includes an etching step, a laser step, a plating step and a singulation step. In the etching step, a plurality of cutting streets of a leadframe are etched. In the laser step, a plastic package material covering on each of the cutting streets is removed via a laser beam. In the plating step, a plurality of plating surfaces are disposed on a plurality of areas of the leadframe without the plastic package material. In the singulation step, the cutting streets of the leadframe are cut to form the package structure.
    Type: Grant
    Filed: February 2, 2023
    Date of Patent: April 9, 2024
    Assignee: INTEGRATED SILICON SOLUTION INC.
    Inventors: Cheng-Fu Yu, Kai-Jih Shih, Yi-Jung Liu
  • Publication number: 20230275804
    Abstract: This disclosure provides a method for establishing a network connection between an intelligent baseboard management controller and a management server. The intelligent baseboard management controller is disposed on a motherboard of an electronic device. A connection configuration program is installed in the electronic device, and the electronic device executes the connection configuration program to transmit a connection information packet to the intelligent baseboard management controller. After receiving the connection information packet, the intelligent baseboard management controller parses a connection information of the management server from the connection information packet, and executes a network connection procedure according to the connection information of the management server, so that the network connection between the intelligent baseboard management controller and the management server is established.
    Type: Application
    Filed: May 27, 2022
    Publication date: August 31, 2023
    Inventors: Shu-ming Chang, Shang-Ju Lin, Yi-Jung Liu
  • Publication number: 20230173615
    Abstract: A method of forming a package structure includes an etching step, a laser step, a plating step and a singulation step. In the etching step, a plurality of cutting streets of a leadframe are etched. In the laser step, a plastic package material covering on each of the cutting streets is removed via a laser beam. In the plating step, a plurality of plating surfaces are disposed on a plurality of areas of the leadframe without the plastic package material. In the singulation step, the cutting streets of the leadframe are cut to form the package structure.
    Type: Application
    Filed: February 2, 2023
    Publication date: June 8, 2023
    Inventors: Cheng-Fu YU, Kai-Jih SHIH, Yi-Jung LIU
  • Patent number: 11612965
    Abstract: A method of forming a package structure includes an etching step, a laser step, a plating step and a singulation step. In the etching step, a plurality of cutting streets of a leadframe are etched. In the laser step, a plastic package material covering on each of the cutting streets is removed via a laser beam. In the plating step, a plurality of plating surfaces are disposed on a plurality of areas of the leadframe without the plastic package material. In the singulation step, the cutting streets of the leadframe are cut to form the package structure.
    Type: Grant
    Filed: December 2, 2020
    Date of Patent: March 28, 2023
    Assignee: INTEGRATED SILICON SOLUTION INC.
    Inventors: Cheng-Fu Yu, Kai-Jih Shih, Yi-Jung Liu
  • Publication number: 20210299791
    Abstract: A method of forming a package structure includes an etching step, a laser step, a plating step and a singulation step. In the etching step, a plurality of cutting streets of a leadframe are etched. In the laser step, a plastic package material covering on each of the cutting streets is removed via a laser beam. In the plating step, a plurality of plating surfaces are disposed on a plurality of areas of the leadframe without the plastic package material. In the singulation step, the cutting streets of the leadframe are cut to form the package structure.
    Type: Application
    Filed: December 2, 2020
    Publication date: September 30, 2021
    Inventors: Cheng-Fu YU, Kai-Jih SHIH, Yi-Jung LIU
  • Publication number: 20210305136
    Abstract: A package structure includes a leadframe, a semiconductor die and a plastic package material. The leadframe includes a die pad and a plurality of leads. The leads are disposed on four sides of the die pad, and each of the leads includes a plurality of plating surfaces. The semiconductor die is disposed on the die pad of the leadframe. The plastic package material is disposed on the leadframe. Each of the leads protrudes an outer region of the plastic package material.
    Type: Application
    Filed: December 2, 2020
    Publication date: September 30, 2021
    Inventors: Cheng-Fu YU, Kai-Jih SHIH, Yi-Jung LIU, Chi-Yi Wu
  • Patent number: 9748175
    Abstract: A method for manufacturing a semiconductor structure is provided. The method for manufacturing a semiconductor structure includes forming an organosilicon layer over a substrate and etching the organosilicon layer to have a trench. The method for manufacturing a semiconductor structure further includes forming a conductive structure in the trench. In addition, the organosilicon layer is made of a material including Si—C bonding and Si—O bonding, and a ratio of an amount of the Si—C bonding to an amount of the Si—O bonding is greater than about 0.2.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: August 29, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Jung Liu, Huan-Wei Wu, Chester Tang, Joung-Wei Liou
  • Patent number: 9282631
    Abstract: Circuit with flat electromagnetic band gap resonance structure, includes a plurality of flat units formed at a conductor layer; each flat unit spirally revolves inward from a first end to an internal point following a rotation direction, and spirally revolves outward from the internal point to a second end following an opposite rotation direction. Each flat unit is connected to a ground plane by a conductive stand (e.g., a via) at a connection point, for suppressing noise resonances at certain frequencies, and the frequencies are related to a stub length of each flat unit, and the stub length is related to a route length from the connection point to an end.
    Type: Grant
    Filed: August 5, 2014
    Date of Patent: March 8, 2016
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Wei Chiu, Yi-Jung Liu, Ling-Chih Chou
  • Publication number: 20150041185
    Abstract: Circuit with flat electromagnetic band gap resonance structure, includes a plurality of flat units formed at a conductor layer; each flat unit spirally revolves inward from a first end to an internal point following a rotation direction, and spirally revolves outward from the internal point to a second end following an opposite rotation direction. Each flat unit is connected to a ground plane by a conductive stand (e.g., a via) at a connection point, for suppressing noise resonances at certain frequencies, and the frequencies are related to a stub length of each flat unit, and the stub length is related to a route length from the connection point to an end.
    Type: Application
    Filed: August 5, 2014
    Publication date: February 12, 2015
    Inventors: Po-Wei Chiu, Yi-Jung Liu, Ling-Chih Chou