Patents by Inventor Yi-Jyun HUANG
Yi-Jyun HUANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220376043Abstract: An integrated circuit includes a substrate, an isolation feature disposed over the substrate, a fin extending from the substrate above the isolation feature, and a gate structure disposed directly over the isolation feature. The integrated circuit further includes a first dielectric layer disposed directly above the isolation feature and adjacent to the gate structure, and a first etch stop layer disposed between the first dielectric layer and the isolation feature. The integrated circuit further includes a second dielectric layer disposed directly above the first dielectric layer, and a second etch stop layer disposed between the first and the second dielectric layers and between the gate structure and the second dielectric layer. The first etch stop layer is also disposed between the gate structure and the second etch stop layer. A conductive feature is directly above the isolation feature and directly contacting the first dielectric layer.Type: ApplicationFiled: August 8, 2022Publication date: November 24, 2022Inventors: Yun Lee, Chen-Ming Lee, Fu-Kai Yang, Yi-Jyun Huang, Sheng-Hsiung Wang, Mei-Yun Wang
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Patent number: 11495494Abstract: An integrated circuit includes a substrate, an isolation feature disposed over the substrate, a fin extending from the substrate alongside the isolation feature such that the fin extends above the isolation feature, and a dielectric layer disposed over the isolation feature. A top surface of the dielectric layer is at a same level as a top surface of the fin or below a top surface of the fin by less than or equal to 15 nanometers.Type: GrantFiled: November 19, 2019Date of Patent: November 8, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yun Lee, Chen-Ming Lee, Fu-Kai Yang, Yi-Jyun Huang, Sheng-Hsiung Wang, Mei-Yun Wang
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Publication number: 20220352341Abstract: The present disclosure describes an exemplary replacement gate process that forms spacer layers in a gate stack to mitigate time dependent dielectric breakdown (TDDB) failures. For example, the method can include a partially fabricated gate structure with a first recess. A spacer layer is deposited into the first recess and etched with an anisotropic etchback (EB) process to form a second recess that has a smaller aperture than the first recess. A metal fill layer is deposited into the second recess.Type: ApplicationFiled: July 20, 2022Publication date: November 3, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Jyun HUANG, Bao-Ru Young, Tung-Heng Hsieh
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Patent number: 11398559Abstract: The present disclosure describes an exemplary replacement gate process that forms spacer layers in a gate stack to mitigate time dependent dielectric breakdown (TDDB) failures. For example, the method can include a partially fabricated gate structure with a first recess. A spacer layer is deposited into the first recess and etched with an anisotropic etchback (EB) process to form a second recess that has a smaller aperture than the first recess. A metal fill layer is deposited into the second recess.Type: GrantFiled: April 16, 2020Date of Patent: July 26, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Jyun Huang, Bao-Ru Young, Tung-Heng Hsieh
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Publication number: 20210226023Abstract: A semiconductor device includes a fin structure, first and second gate structures, a source/drain region, a source/drain contact layer and a separation layer. The fin structure protrudes from an isolation insulating layer disposed over a substrate and extends in a first direction. The first and second gate structures are formed over the fin structure and extend in a second direction crossing the first direction. The source/drain region is disposed between the first and second gate structures. The interlayer insulating layer is disposed over the fin structure, the first and second gate structures and the source/drain region. The first source/drain contact layer is disposed on the first source/drain region. The separation layer is disposed adjacent to the first source/drain contact layer. Ends of the first and second gate structures and an end of the source drain contact layer are in contact with a same face of the separation layer.Type: ApplicationFiled: April 5, 2021Publication date: July 22, 2021Inventors: Yi-Jyun HUANG, Tung-Heng HSIEH, Bao-Ru YOUNG
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Patent number: 11062945Abstract: A method includes providing a device structure having an isolation structure, a fin adjacent the isolation structure and taller than the isolation structure, and gate structures over the fin and the isolation structure. The isolation structure, the fin, and the gate structures define a first trench over the fin and a second trench over the isolation structure. The method further includes forming a first contact etch stop layer (CESL) over the gate structures, the fin, and the isolation structure; depositing a first inter-layer dielectric (ILD) layer over the first CESL and filling in the first and second trenches; and recessing the first ILD layer such that the first ILD layer in the first trench is removed and the first ILD layer in the second trench is recessed to a level that is about even with a top surface of the fin.Type: GrantFiled: November 27, 2018Date of Patent: July 13, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yun Lee, Chen-Ming Lee, Fu-Kai Yang, Yi-Jyun Huang, Sheng-Hsiung Wang, Mei-Yun Wang
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Patent number: 10971588Abstract: A semiconductor device includes a fin structure, first and second gate structures, a source/drain region, a source/drain contact layer and a separation layer. The fin structure protrudes from an isolation insulating layer disposed over a substrate and extends in a first direction. The first and second gate structures are formed over the fin structure and extend in a second direction crossing the first direction. The source/drain region is disposed between the first and second gate structures. The interlayer insulating layer is disposed over the fin structure, the first and second gate structures and the source/drain region. The first source/drain contact layer is disposed on the first source/drain region. The separation layer is disposed adjacent to the first source/drain contact layer. Ends of the first and second gate structures and an end of the source drain contact layer are in contact with a same face of the separation layer.Type: GrantFiled: October 11, 2019Date of Patent: April 6, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Jyun Huang, Tung-Heng Hsieh, Bao-Ru Young
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Publication number: 20200243663Abstract: The present disclosure describes an exemplary replacement gate process that forms spacer layers in a gate stack to mitigate time dependent dielectric breakdown (TDDB) failures. For example, the method can include a partially fabricated gate structure with a first recess. A spacer layer is deposited into the first recess and etched with an anisotropic etchback (EB) process to form a second recess that has a smaller aperture than the first recess. A metal fill layer is deposited into the second recess.Type: ApplicationFiled: April 16, 2020Publication date: July 30, 2020Applicant: Taiwan Semiconductor Manufacturing, Co., Ltd.Inventors: Yi-Jyun Huang, Bao-Ru Young, Tung-Heng Hsieh
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Patent number: 10685880Abstract: A method includes providing a device structure having an isolation structure, a fin adjacent the isolation structure and taller than the isolation structure, and gate structures over the fin and the isolation structure. The isolation structure, the fin, and the gate structures define a first trench over the fin and a second trench over the isolation structure. The method further includes forming a first contact etch stop layer (CESL) over the gate structures, the fin, and the isolation structure; depositing a first inter-layer dielectric (ILD) layer over the first CESL and filling in the first and second trenches; and recessing the first ILD layer such that the first ILD layer in the first trench is removed and the first ILD layer in the second trench is recessed to a level that is about even with a top surface of the fin.Type: GrantFiled: August 30, 2017Date of Patent: June 16, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yun Lee, Chen-Ming Lee, Fu-Kai Yang, Yi-Jyun Huang, Sheng-Hsiung Wang, Mei-Yun Wang
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Patent number: 10658486Abstract: The present disclosure describes an exemplary replacement gate process that forms spacer layers in a gate stack to mitigate time dependent dielectric breakdown (TDDB) failures. For example, the method can include a partially fabricated gate structure with a first recess. A spacer layer is deposited into the first recess and etched with an anisotropic etchback (EB) process to form a second recess that has a smaller aperture than the first recess. A metal fill layer is deposited into the second recess.Type: GrantFiled: May 18, 2017Date of Patent: May 19, 2020Assignee: Taiwan Semiconductor Manufacutring Co., Ltd.Inventors: Yi-Jyun Huang, Bao-Ru Young, Tung-Heng Hsieh
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Publication number: 20200098632Abstract: An integrated circuit includes a substrate, an isolation feature disposed over the substrate, a fin extending from the substrate alongside the isolation feature such that the fin extends above the isolation feature, and a dielectric layer disposed over the isolation feature. A top surface of the dielectric layer is at a same level as a top surface of the fin or below a top surface of the fin by less than or equal to 15 nanometers.Type: ApplicationFiled: November 19, 2019Publication date: March 26, 2020Inventors: Yun Lee, Chen-Ming Lee, Fu-Kai Yang, Yi-Jyun Huang, Sheng-Hsiung Wang, Mei-Yun Wang
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Publication number: 20200044038Abstract: A semiconductor device includes a fin structure, first and second gate structures, a source/drain region, a source/drain contact layer and a separation layer. The fin structure protrudes from an isolation insulating layer disposed over a substrate and extends in a first direction. The first and second gate structures are formed over the fin structure and extend in a second direction crossing the first direction. The source/drain region is disposed between the first and second gate structures. The interlayer insulating layer is disposed over the fin structure, the first and second gate structures and the source/drain region. The first source/drain contact layer is disposed on the first source/drain region. The separation layer is disposed adjacent to the first source/drain contact layer. Ends of the first and second gate structures and an end of the source drain contact layer are in contact with a same face of the separation layer.Type: ApplicationFiled: October 11, 2019Publication date: February 6, 2020Inventors: Yi-Jyun HUANG, Tung-Heng HSIEH, Bao-Ru YOUNG
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Patent number: 10522634Abstract: A semiconductor device includes a fin structure, first and second gate structures, a source/drain region, a source/drain contact layer and a separation layer. The fin structure protrudes from an isolation insulating layer disposed over a substrate and extends in a first direction. The first and second gate structures are formed over the fin structure and extend in a second direction crossing the first direction. The source/drain region is disposed between the first and second gate structures. The interlayer insulating layer is disposed over the fin structure, the first and second gate structures and the source/drain region. The first source/drain contact layer is disposed on the first source/drain region. The separation layer is disposed adjacent to the first source/drain contact layer. Ends of the first and second gate structures and an end of the source drain contact layer are in contact with a same face of the separation layer.Type: GrantFiled: July 30, 2018Date of Patent: December 31, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Jyun Huang, Tung-Heng Hsieh, Bao-Ru Young
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Patent number: 10340348Abstract: A semiconductor device includes a fin structure, first and second gate structures, a source/drain region, a source/drain contact layer and a separation layer. The fin structure protrudes from an isolation insulating layer disposed over a substrate and extends in a first direction. The first and second gate structures are formed over the fin structure and extend in a second direction crossing the first direction. The source/drain region is disposed between the first and second gate structures. The interlayer insulating layer is disposed over the fin structure, the first and second gate structures and the source/drain region. The first source/drain contact layer is disposed on the first source/drain region. The separation layer is disposed adjacent to the first source/drain contact layer. Ends of the first and second gate structures and an end of the source drain contact layer are in contact with a same face of the separation layer.Type: GrantFiled: May 17, 2016Date of Patent: July 2, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Jyun Huang, Tung-Heng Hsieh, Bao-Ru Young
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Publication number: 20190096760Abstract: A method includes providing a device structure having an isolation structure, a fin adjacent the isolation structure and taller than the isolation structure, and gate structures over the fin and the isolation structure. The isolation structure, the fin, and the gate structures define a first trench over the fin and a second trench over the isolation structure. The method further includes forming a first contact etch stop layer (CESL) over the gate structures, the fin, and the isolation structure; depositing a first inter-layer dielectric (ILD) layer over the first CESL and filling in the first and second trenches; and recessing the first ILD layer such that the first ILD layer in the first trench is removed and the first ILD layer in the second trench is recessed to a level that is about even with a top surface of the fin.Type: ApplicationFiled: November 27, 2018Publication date: March 28, 2019Inventors: Yun Lee, Chen-Ming Lee, Fu-Kai Yang, Yi-Jyun Huang, Sheng-Hsiung Wang, Mei-Yun Wang
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Publication number: 20190067099Abstract: A method includes providing a device structure having an isolation structure, a fin adjacent the isolation structure and taller than the isolation structure, and gate structures over the fin and the isolation structure. The isolation structure, the fin, and the gate structures define a first trench over the fin and a second trench over the isolation structure. The method further includes forming a first contact etch stop layer (CESL) over the gate structures, the fin, and the isolation structure; depositing a first inter-layer dielectric (ILD) layer over the first CESL and filling in the first and second trenches; and recessing the first ILD layer such that the first ILD layer in the first trench is removed and the first ILD layer in the second trench is recessed to a level that is about even with a top surface of the fin.Type: ApplicationFiled: August 30, 2017Publication date: February 28, 2019Inventors: Yun Lee, Chen-Ming Lee, Fu-Kai Yang, Yi-Jyun Huang, Sheng-Hsiung Wang, Mei-Yun Wang
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Patent number: 10164034Abstract: A semiconductor device includes a fin structure, first and second gate structures, a source/drain region, a source/drain contact, a separator, a plug contacting the source/drain contact and a wiring contacting the plug. The fin structure protrudes from an isolation insulating layer and extends in a first direction. The first and second gate structures are formed over the fin structure and extend in a second direction crossing the first direction. The source/drain region is disposed between the first and second gate structures. The interlayer insulating layer is disposed over the fin structure, the first and second gate structures and the source/drain region. The first source/drain contact is disposed on the first source/drain region. The separator is disposed adjacent to the first source/drain contact layer. Ends of the first and second gate structures and an end of the source drain contact are in contact with a same face of the separator.Type: GrantFiled: July 12, 2017Date of Patent: December 25, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Yi-Jyun Huang, Tung-Heng Hsieh, Bao-Ru Young
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Publication number: 20180350928Abstract: A semiconductor device includes a fin structure, first and second gate structures, a source/drain region, a source/drain contact layer and a separation layer. The fin structure protrudes from an isolation insulating layer disposed over a substrate and extends in a first direction. The first and second gate structures are formed over the fin structure and extend in a second direction crossing the first direction. The source/drain region is disposed between the first and second gate structures. The interlayer insulating layer is disposed over the fin structure, the first and second gate structures and the source/drain region. The first source/drain contact layer is disposed on the first source/drain region. The separation layer is disposed adjacent to the first source/drain contact layer. Ends of the first and second gate structures and an end of the source drain contact layer are in contact with a same face of the separation layer.Type: ApplicationFiled: July 30, 2018Publication date: December 6, 2018Inventors: Yi-Jyun HUANG, Tung-Heng HSIEH, Bao-Ru YOUNG
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Publication number: 20180337053Abstract: The present disclosure describes an exemplary replacement gate process that forms spacer layers in a gate stack to mitigate time dependent dielectric breakdown (TDDB) failures. For example, the method can include a partially fabricated gate structure with a first recess. A spacer layer is deposited into the first recess and etched with an anisotropic etchback (EB) process to form a second recess that has a smaller aperture than the first recess. A metal fill layer is deposited into the second recess.Type: ApplicationFiled: May 18, 2017Publication date: November 22, 2018Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Jyun HUANG, Bao-Ru YOUNG, Tung-Heng HSIEH
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Publication number: 20170309715Abstract: A semiconductor device includes a fin structure, first and second gate structures, a source/drain region, a source/drain contact, a separator, a plug contacting the source/drain contact and a wiring contacting the plug. The fin structure protrudes from an isolation insulating layer and extends in a first direction. The first and second gate structures are formed over the fin structure and extend in a second direction crossing the first direction. The source/drain region is disposed between the first and second gate structures. The interlayer insulating layer is disposed over the fin structure, the first and second gate structures and the source/drain region. The first source/drain contact is disposed on the first source/drain region. The separator is disposed adjacent to the first source/drain contact layer. Ends of the first and second gate structures and an end of the source drain contact are in contact with a same face of the separator.Type: ApplicationFiled: July 12, 2017Publication date: October 26, 2017Inventors: Yi-Jyun HUANG, Tung-Heng HSIEH, Bao-Ru YOUNG