Patents by Inventor Yi-Kai HSIAO

Yi-Kai HSIAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240405065
    Abstract: A method of manufacturing a semiconductor device is provided, including: forming a first conductive type lightly doped region in the epitaxial layer; forming a first conductive type heavily doped region and a second conductive type heavily doped region in the epitaxial layer on the first conductive type lightly doped region, in which the neighboring first conductive type heavily doped regions are spaced apart by the second conductive type heavily doped region; disposing the mask on the second conductive type heavily doped region; disposing a spacer on a sidewall of the mask; doping a first conductive type dopant in the first conductive type lightly doped region to form an anti-breakdown region; removing the mask and forming a trench extending into the second conductive type heavily doped region, first conductive type lightly doped region and the epitaxial layer; and removing the spacer.
    Type: Application
    Filed: May 30, 2024
    Publication date: December 5, 2024
    Inventors: Chia-Lung HUNG, Yi-Kai HSIAO, Hao-Chung KUO
  • Publication number: 20240379843
    Abstract: A method of forming a semiconductor device includes forming an epitaxial layer on a substrate, forming a hard mask layer on the epitaxial layer, forming a JFET region in the epitaxial layer by using the hard mask layer and removing the hard mask layer, forming a staircase-shaped hard mask stack on the JFET region, forming a well region in the epitaxial layer by using the staircase-shaped hard mask stack, in which a bottom of the JFET region is lower than a bottom of the well region and the bottom of the well region is in contact with the JFET region and a drift region of the epitaxial layer simultaneously, forming a source region in the well region, removing the staircase-shaped hard mask stack, and forming a gate structure on the JFET region.
    Type: Application
    Filed: April 30, 2024
    Publication date: November 14, 2024
    Inventors: Yi-Kai HSIAO, Chia-Lung HUNG, Hao-Chung KUO
  • Publication number: 20240379844
    Abstract: A method of manufacturing a semiconductor device includes forming an epitaxial layer on a substrate, forming a hard mask on the epitaxial layer, in which the hard mask includes a first portion and a second portion, with a gap therebetween, performing an oxidation process to form an oxide layer on a surface of the hard mask, forming a source region in the epitaxial layer through the gap of the hard mask, forming a well region in the epitaxial layer using the second portion of the hard mask as a mask, forming a sacrificial layer on the source region and the well region, removing the second portion of the hard mask, forming a JFET region in the epitaxial layer using the sacrificial layer as a mask, forming a dielectric layer on the JFET region, removing the sacrificial layer and forming a gate structure adjacent the dielectric layer.
    Type: Application
    Filed: May 1, 2024
    Publication date: November 14, 2024
    Inventors: Chia-Lung HUNG, Yi-Kai HSIAO, Hao-Chung KUO
  • Publication number: 20240297250
    Abstract: A method of manufacturing a semiconductor device includes providing a substrate, in which the substrate is SiC base. The substrate, from bottom to top, sequentially includes an N-type heavy doping base layer, an N-type light doping layer, a P-well region, and an N-type heavy doping layer. The substrate is etched by using a patterned mask to form a gate trench and a channel region defined by the gate trench. The channel region is shielded by the patterned mask. An ion implant is performed to the gate trench such that a shielding implant layer is formed on the bottom of the gate trench. An oxidation process is performed to the gate trench thereby forming a gate oxide layer. The oxidation rate at the bottom of the gate trench is faster than the oxidation rate at the sidewall of the gate trench. A semiconductor device is also provided.
    Type: Application
    Filed: March 1, 2024
    Publication date: September 5, 2024
    Inventors: Chia-Lung HUNG, Yi-Kai HSIAO, Hao-Chung KUO
  • Publication number: 20240097019
    Abstract: A semiconductor device includes a substrate, an epitaxial layer, a well region, a source region, a base region, a first JFET region, a second JFET region, a gate dielectric layer and a gate layer. The epitaxial layer is at a side of the substrate. The well region is in the epitaxial layer. The source region is in the well region. The base region is in the well region and adjacent to the source region. The first JFET region is adjacent to the well region. The second JFET region is in the first JFET region. A doping concentration of the second JFET region is higher than a doping concentration of the first JFET region. The gate dielectric layer is at a side of the epitaxial layer away from the substrate. The gate layer is at a side of the gate dielectric layer away from the epitaxial layer.
    Type: Application
    Filed: September 15, 2023
    Publication date: March 21, 2024
    Inventors: Yi-Kai HSIAO, Kuang-Hao CHIANG, Hao-Chung KUO
  • Publication number: 20240038874
    Abstract: A manufacturing method of a semiconductor device includes the following steps. A base region is formed in a substrate. A protective layer is formed on the substrate and covers the base region. First and second sacrificial layers are formed on the substrate and cover the protective layer. A source region, a well region, and a junction field effect transistor (JFET) region are formed in the substrate. When the source region, the well region, and the JFET region are formed in sequence, the source region and the well region are formed by the first sacrificial layer, and the JFET region is formed by the second sacrificial layer. When the JFET region, the well region, and the source region are formed in sequence, the JFET region is formed by the first sacrificial layer, and the well region and the source region are formed by the second sacrificial layer.
    Type: Application
    Filed: July 28, 2023
    Publication date: February 1, 2024
    Inventors: Yi-Kai HSIAO, Kuang-Hao CHIANG, Hao-Chung KUO
  • Publication number: 20240006486
    Abstract: A method of forming a semiconductor device includes forming a P-type heavily doped region in a substrate. A sacrificial layer is formed on the substrate and covers the P-type heavily doped region. The sacrificial layer is patterned, so that sidewalls of the sacrificial layer are above the substrate inside the P-type heavily doped region. An N-type heavily doped region adjacent to the P-type heavily doped region is formed in the substrate by using the sacrificial layer as mask. A wet etching process is performed to retract the sidewalls of the sacrificial layer to the substrate inside the N-type heavily doped region. A P-type lightly doped region is formed in the substrate by using the sacrificial layer as mask. The P-type lightly doped region is adjacent to the N-type heavily doped region, and is in contact with bottoms of the P-type heavily doped region and the N-type heavily doped region.
    Type: Application
    Filed: June 30, 2023
    Publication date: January 4, 2024
    Inventors: Yi-Kai HSIAO, Wen-Cheng HSU, Kuang-Hao CHIANG, Hao-Chung KUO