Patents by Inventor Yi-Kai TSENG

Yi-Kai TSENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250158415
    Abstract: The present disclosure relates to a power grid system and method of managing the same. According to the present invention, a power grid system is provided. The power grid system is adapted to supply electric power to at least one load unit, and the power grid system comprises a bus, a switching module, and an energy storage system coupled to the bus. The at least one load unit is coupled to the bus. The switching module comprises a switching device. The switching device is connected between the bus and a main grid. The energy storage system is configured to operate in a current source mode and a voltage source mode, and it is configured to receive a tripped signal from the switching module. The energy storage system is configured to switch to the voltage source mode when the energy storage system receives the tripped signal.
    Type: Application
    Filed: November 15, 2023
    Publication date: May 15, 2025
    Inventors: YI-KUAN KE, CHIA-CHING LIN, YI-KAI TSENG, CHIH-HAN KO
  • Patent number: 9831343
    Abstract: A semiconductor device having n-type field-effect-transistor (NFET) structure and a method of fabricating the same are provided. The NFET structure of the semiconductor device includes a silicon substrate, at least one source/drain portion and a cap layer. The source/drain portion can be disposed within the silicon substrate, and the source/drain portion comprises at least one n-type dopant-containing portion. The cap layer overlies and covers the source/drain portion, and the cap layer includes silicon carbide (SiC) or silicon germanium (SiGe) with relatively low germanium concentration, thereby preventing n-type dopants in the at least one n-type dopant-containing portion of the source/drain portion from being degraded after sequent thermal and cleaning processes.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: November 28, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chii-Horng Li, Chien-I Kuo, Lilly Su, Chien-Chang Su, Yi-Kai Tseng, Ying-Wei Li
  • Publication number: 20170194495
    Abstract: A semiconductor device having n-type field-effect-transistor (NFET) structure and a method of fabricating the same are provided. The NFET structure of the semiconductor device includes a silicon substrate, at least one source/drain portion and a cap layer. The source/drain portion can be disposed within the silicon substrate, and the source/drain portion comprises at least one n-type dopant-containing portion. The cap layer overlies and covers the source/drain portion, and the cap layer includes silicon carbide (SiC) or silicon germanium (SiGe) with relatively low germanium concentration, thereby preventing n-type dopants in the at least one n-type dopant-containing portion of the source/drain portion from being degraded after sequent thermal and cleaning processes.
    Type: Application
    Filed: December 30, 2015
    Publication date: July 6, 2017
    Inventors: Chii-Horng Ll, Chien-l KUO, Lilly SU, Chien-Chang SU, Yi-Kai TSENG, Ying-Wei LI