Patents by Inventor Yi-Kan Cheng

Yi-Kan Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200357786
    Abstract: An integrated circuit structure includes: an integrated circuit structure includes: a first plurality of cell rows extending in a first direction, and a second plurality of cell rows extending in the first direction. Each of the first plurality of cell rows has a first row height and comprises a plurality of first cells disposed therein. Each of the second plurality of cell rows has a second row height different from the first row height and comprises a plurality of second cells disposed therein. The plurality of first cells comprises a first plurality of active regions each of which continuously extends across the plurality of first cells in the first direction. The plurality of second cells comprises a second plurality of active regions each of which continuously extends across the plurality of second cells in the first direction. At least one active region of the first and second pluralities of active regions has a width varying along the first direction.
    Type: Application
    Filed: May 26, 2020
    Publication date: November 12, 2020
    Inventors: Kam-Tou SIO, Jiann-Tyng Tzeng, Chung-Hsing Wang, Yi-Kan Cheng
  • Patent number: 10811316
    Abstract: A method for forming an integrated circuit (IC) is provided. The method includes the following operations. A circuit layout including a first load region and a second load region is received. A full power network of the circuit layout is obtained. The full power network is transformed into a first power network according to the first load region. A first power simulation is performed upon the first power network. The full power network is transformed into a second power network according to the second load region. A second power simulation is performed upon the second power network. The IC is fabricated according to the circuit layout.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: October 20, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ka Fai Chang, Fong-Yuan Chang, Chin-Chou Liu, Yi-Kan Cheng
  • Publication number: 20200328202
    Abstract: Standard cell libraries include one or more standard cells and one or more corresponding standard cell variations. The one or more standard cell variations are different from their one or more standard cells in terms of geometric shapes, locations of the geometric shapes, and/or interconnections between the geometric shapes. The exemplary systems and methods described herein selectively choose from among the one or more standard cells and/or the one or more standard cell variations to form an electronic architectural design for an electronic device. In some situations, some of the one or more standard cells are unable to satisfy one or more electronic design constraints imposed by a semiconductor foundry and/or semiconductor technology node when placed onto the electronic device design real estate. In these situations, the one or more standard cell variations corresponding to these standard cells are placed onto the electronic device design real estate.
    Type: Application
    Filed: June 25, 2020
    Publication date: October 15, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Hsiung CHEN, Jerry Chang-Jui KAO, Fong-Yuan CHANG, Po-Hsiang HUANG, Shao-Huan WANG, XinYong WANG, Yi-Kan CHENG, Chun-Chen CHEN
  • Patent number: 10763253
    Abstract: A structure and method for cooling a three-dimensional integrated circuit (3DIC) are provided. A cooling element is configured for thermal connection to the 3DIC. The cooling element includes a plurality of individually controllable cooling modules disposed at a first plurality of locations relative to the 3DIC. Each of the cooling modules includes a cold pole and a heat sink. The cold pole is configured to absorb heat from the 3DIC. The heat sink is configured to dissipate the heat absorbed by the cold pole and is coupled to the cold pole via an N-type semiconductor element and via a P-type semiconductor element. A temperature sensing element includes a plurality of thermal monitoring elements disposed at a second plurality of locations relative to the 3DIC for measuring temperatures at the second plurality of locations. The measured temperatures control the plurality of cooling modules.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: September 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hui-Yu Lee, Chi-Wen Chang, Jui-Feng Kuan, Yi-Kan Cheng
  • Patent number: 10741539
    Abstract: Standard cell libraries include one or more standard cells and one or more corresponding standard cell variations. The one or more standard cell variations are different from their one or more standard cells in terms of geometric shapes, locations of the geometric shapes, and/or interconnections between the geometric shapes. The exemplary systems and methods described herein selectively choose from among the one or more standard cells and/or the one or more standard cell variations to form an electronic architectural design for an electronic device. In some situations, some of the one or more standard cells are unable to satisfy one or more electronic design constraints imposed by a semiconductor foundry and/or semiconductor technology node when placed onto the electronic device design real estate. In these situations, the one or more standard cell variations corresponding to these standard cells are placed onto the electronic device design real estate.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: August 11, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Hsiung Chen, Jerry Chang-Jui Kao, Fong-Yuan Chang, Po-Hsiang Huang, Shao-Huan Wang, XinYong Wang, Yi-Kan Cheng, Chun-Chen Chen
  • Patent number: 10678990
    Abstract: In some embodiments, an initial circuit arrangement is provided. The initial circuit arrangement includes cells that include default-rule lines and non-default-rule lines. Line widths of the default-rule lines are selectively increased for a first cell in the initial circuit arrangement, thereby providing a first modified circuit arrangement. A first maximum capacitance value is calculated for the first cell of the first modified circuit arrangement. A second modified circuit arrangement is provided by selectively increasing line widths of the non-default-rule lines in the first modified circuit arrangement. A second maximum capacitance value is calculated for the first cell of the second modified circuit arrangement. A line width of a first non-default-rule line is selectively reduced based on whether the first maximum capacitance value adheres to a predetermined relationship with the second maximum capacitance value. The second modified circuit arrangement is manufactured on a semiconductor substrate.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: June 9, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Nan Yang, Chung-Hsing Wang, Yi-Kan Cheng, Kumar Lalgudi
  • Publication number: 20200175220
    Abstract: A method of a layout diagram (of a conductive line structure for an IC) including: for a first set of pillar patterns included in an initial layout diagram that represents portions of an M(i) layer of metallization and where i is a non-negative number, the first set including first and second pillar patterns which are non-overlapping of each other, which have long axes that are substantially collinear with a reference line, and which have a first distance of separation, determining a first distance of separation as between corresponding immediately adjacent members of the first set; recognizing that the first distance is less than a transverse routing (TVR) separation threshold for an M(i+j) layer of metallization, where j is an integer and j?2; and increasing the first distance so as to become a second distance which is greater than the TVR separation threshold of the M(i+j) layer.
    Type: Application
    Filed: November 27, 2019
    Publication date: June 4, 2020
    Inventors: Hiranmay BISWAS, Chung-Hsing WANG, Kuo-Nan YANG, Yi-Kan CHENG
  • Publication number: 20200168527
    Abstract: A device, such as a computer system, includes an interconnection device die and at least two additional device dice. The additional device dies can be system on integrated chip (SOIC) dies laying face to face (F2F) on the interconnection device die. The interconnection device die includes electrical connectors on one surface, enabling connection to and/or among the additional device dice. The interconnection device die includes at least one redistribution circuit structure, which may be an integrated fan out (InFO) structure, and at least one through-silicon via (TSV). The TSV enables connection between a signal line, power line or ground line, from an opposite surface of the interconnection device die to the redistribution circuit structure and/or electrical connectors. At least one of the additional dice can be a three-dimensional integrated circuit (3DIC) die with face to back (F2B) stacking.
    Type: Application
    Filed: September 6, 2019
    Publication date: May 28, 2020
    Applicant: Taiwan Semiconductor Manfacturing Co., Ltd.
    Inventors: Fong-Yuan CHANG, Chin-Chou LIU, Chin-Her CHIEN, Cheny-hung YEH, Hui Yu LEE, Po-Hsiang HUANG, Yi-Kan CHENG
  • Publication number: 20200151382
    Abstract: A method of making a semiconductor device includes determining a temperature profile for a first die of a three-dimensional integrated circuit (3DIC), wherein the first die comprises a plurality of sub-regions of the first die based on the determined temperature profile. The method further includes simulating operation of a circuit in a second die of the 3DIC based on the determined temperature profile and a corresponding sub-region of the plurality of sub-regions.
    Type: Application
    Filed: January 16, 2020
    Publication date: May 14, 2020
    Inventors: Chi-Wen CHANG, Hui Yu LEE, Ya Yun LIU, Jui-Feng KUAN, Yi-Kan CHENG
  • Publication number: 20200135388
    Abstract: An entangled inductor structure generates opposite polarity internal magnetic fields therein to substantially reduce, or cancel, external magnetic fields propagating outside of the entangled inductor structure. These reduced external magnetic fields propagating outside of the entangled inductor structure effectively reduce a keep out zone (KOZ) between the entangled inductor structure and other electrical, mechanical, and/or electro-mechanical components. This allows the entangled inductor structure to be situated closer to these other electrical, mechanical, and/or electro-mechanical components within the IC as compared to conventional inductors which generate larger external magnetic fields.
    Type: Application
    Filed: June 28, 2019
    Publication date: April 30, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ka Fai CHANG, Chin-Chou LIU, Fong-Yuan CHANG, Hui Yu LEE, Yi-Kan CHENG
  • Publication number: 20200134125
    Abstract: A method of generating a layout diagram including a first level of metallization (M_1st level) including: identifying, in the layout diagram, a filler cell and a first functional cell substantially abutting the filler cell; the first functional cell including first and second side boundaries, first wiring patterns in the M_1st level, and representing corresponding first conductors in the first functional cell region; and first and second groups of cut patterns overlying corresponding portions of the first wiring patterns and being substantially aligned with the corresponding first and second side boundaries; adjusting one or more locations of corresponding one or more selected cut patterns of the second group thereby correspondingly elongating one or more selected ones of the first wiring patterns so as to be corresponding first elongated wiring patterns which extend across the second boundary of the first functional cell into the filler cell.
    Type: Application
    Filed: October 24, 2019
    Publication date: April 30, 2020
    Inventors: Po-Hsiang HUANG, Chin-Chou LIU, Sheng-Hsiung CHEN, Fong-Yuan CHANG, Hui-Zhong ZHUANG, Meng-Hsueh WANG, Yi-Kan CHENG, Chun-Chen CHEN
  • Publication number: 20200134124
    Abstract: A method (of generating a layout diagram) includes generating a cell, representing at least part of a circuit in a semiconductor device, which is arranged at least in part according to second tracks of the M_2nd level (M_2nd tracks), and first tracks of the M_1st level (M_1st tracks). The generating the cell includes: selecting, based on a chosen site for the cell in the layout diagram, one of the M_2nd tracks; generating a first M_2nd pin pattern representing an output pin of the circuit; arranging a long axis of the first pin pattern substantially along the selected M_2nd track; generating second, third, fourth and fifth M_1st pin patterns representing corresponding input pins of the circuit; and arranging long axes of the second to fifth pin patterns substantially along corresponding ones of the M_1st tracks.
    Type: Application
    Filed: October 21, 2019
    Publication date: April 30, 2020
    Inventors: Pin-Dai SUE, Chin-Chou LIU, Sheng-Hsiung CHEN, Fong-Yuan CHANG, Lee-Chung LU, Yen-Hung LIN, Li-Chun TIEN, Po-Hsiang HUANG, Yi-Kan CHENG, Chi-Yu LU
  • Publication number: 20200051863
    Abstract: A method for forming an integrated circuit (IC) is provided. The method includes the following operations. A circuit layout including a first load region and a second load region is received. A full power network of the circuit layout is obtained. The full power network is transformed into a first power network according to the first load region. A first power simulation is performed upon the first power network. The full power network is transformed into a second power network according to the second load region. A second power simulation is performed upon the second power network. The IC is fabricated according to the circuit layout.
    Type: Application
    Filed: August 13, 2018
    Publication date: February 13, 2020
    Inventors: KA FAI CHANG, FONG-YUAN CHANG, CHIN-CHOU LIU, YI-KAN CHENG
  • Patent number: 10540475
    Abstract: A system including a memory; and a simulation tool connected to the memory. The simulation tool is configured to receive information related to a plurality of dies. The simulation tool is further configured to receive a plurality of input vectors. The simulation tool is further configured to determining a temperature profile for a first die of the plurality of dies. The simulation tool is further configured to simulate operation of a second die of the plurality of dies based on the determined temperature profile and the received plurality of input vectors.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: January 21, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Wen Chang, Hui Yu Lee, Ya Yun Liu, Jui-Feng Kuan, Yi-Kan Cheng
  • Publication number: 20200006325
    Abstract: A structure and method for cooling a three-dimensional integrated circuit (3DIC) are provided. A cooling element is configured for thermal connection to the 3DIC. The cooling element includes a plurality of individually controllable cooling modules disposed at a first plurality of locations relative to the 3DIC. Each of the cooling modules includes a cold pole and a heat sink. The cold pole is configured to absorb heat from the 3DIC. The heat sink is configured to dissipate the heat absorbed by the cold pole and is coupled to the cold pole via an N-type semiconductor element and via a P-type semiconductor element. A temperature sensing element includes a plurality of thermal monitoring elements disposed at a second plurality of locations relative to the 3DIC for measuring temperatures at the second plurality of locations. The measured temperatures control the plurality of cooling modules.
    Type: Application
    Filed: September 12, 2019
    Publication date: January 2, 2020
    Inventors: Hui Yu Lee, Chi-Wen Chang, Jui-Feng Kuan, Yi-Kan Cheng
  • Patent number: 10515178
    Abstract: A method (of generating a layout diagram of a conductive line structure includes: determining that a first set of first to fourth short pillar patterns (which represent portions of an M(i) layer of metallization and are located relative to a grid), violates a minimum transverse-routing (TVR) distance of alpha-direction-separation, wherein (1) the grid has orthogonal alpha and beta tracks, and (2) the short pillar patterns have long axes which are substantially co-track aligned with a first one of the alpha tracks and have a first distance (of alpha-direction-separation between immediately adjacent members of the first set) which is less than the TVR distance; and merging pairings of the first & second and third & fourth short pillar patterns into corresponding first and second medium pillar patterns which have a second distance of alpha-direction-separation therebetween; the second value being greater than the TVR distance.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hiranmay Biswas, Chung-Hsing Wang, Kuo-Nan Yang, Yi-Kan Cheng
  • Publication number: 20190286784
    Abstract: A method (of generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks, the layout diagram being stored on a non-transitory computer-readable medium) includes: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in at least one of a non-circular group or a cyclic group which violates a design rule; and temporarily preventing, if there is a violation, placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.
    Type: Application
    Filed: March 12, 2019
    Publication date: September 19, 2019
    Inventors: Fong-Yuan CHANG, Chin-Chou LIU, Hui-Zhong ZHUANG, Meng-Kai HSU, Pin-Dai SUE, Po-Hsiang HUANG, Yi-Kan CHENG, Chi-Yu LU, Jung-Chou TSAI
  • Patent number: 10396063
    Abstract: In some embodiments, a first cell layout and a second cell layout are provided and combined into a third cell layout. Each of the first cell layout and the second cell layout includes a higher power line, a lower power line, an output pin, at least one up transistor and at least one down transistor formed to electrically couple the output pin to the higher power line and the output pin to the lower power line, respectively. The at least one up transistor and the at least one down transistor of the second cell layout include a gate line. For the combining, the gate line is non-selectively electrically coupled to the output pin of the first cell layout to form a first node. A design layout in which the third cell layout is used at different locations is generated.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: August 27, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Fong-Yuan Chang, Lee-Chung Lu, Yi-Kan Cheng, Sheng-Hsiung Chen, Po-Hsiang Huang, Shun Li Chen, Jeo-Yen Lee, Jyun-Hao Chang, Shao-Huan Wang, Chien-Ying Chen
  • Publication number: 20190108304
    Abstract: In some embodiments, an initial circuit arrangement is provided. The initial circuit arrangement includes cells that include default-rule lines and non-default-rule lines. Line widths of the default-rule lines are selectively increased for a first cell in the initial circuit arrangement, thereby providing a first modified circuit arrangement. A first maximum capacitance value is calculated for the first cell of the first modified circuit arrangement. A second modified circuit arrangement is provided by selectively increasing line widths of the non-default-rule lines in the first modified circuit arrangement. A second maximum capacitance value is calculated for the first cell of the second modified circuit arrangement. A line width of a first non-default-rule line is selectively reduced based on whether the first maximum capacitance value adheres to a predetermined relationship with the second maximum capacitance value. The second modified circuit arrangement is manufactured on a semiconductor substrate.
    Type: Application
    Filed: November 30, 2018
    Publication date: April 11, 2019
    Inventors: Kuo-Nan Yang, Chung-Hsing Wang, Yi-Kan Cheng, Kumar Lalgudi
  • Publication number: 20190064770
    Abstract: Exemplary embodiments for multiple standard cell libraries are disclosed that include one or more standard cells and one or more corresponding standard cell variations. The one or more standard cell variations have similar functionality as their one or more standard cells but are different from their one or more standard cells in terms of geometric shapes, locations of the geometric shapes, and/or interconnections between the geometric shapes. The exemplary systems and methods described herein selectively choose from among the one or more standard cells and/or the one or more standard cell variations to form an electronic architectural design for analog circuitry and/or digital circuitry of an electronic device. In an exemplary embodiment, a semiconductor foundry and/or semiconductor technology node can impose one or more electronic design constraints on the placement of the one or more standard cells onto an electronic device design real estate.
    Type: Application
    Filed: November 1, 2017
    Publication date: February 28, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Hsiung CHEN, Jerry Chang-Jui Kao, Fong-Yuan Chang, Po-Hsiang Huang, Shao-Huan Wang, XinYong Wang, Yi-Kan Cheng, Chun-Chen Chen