Abstract: A printed circuit board includes a signal layer, an insulation layer, and a reference layer. A transmission line is located on the signal layer. A test point is located on the transmission line. A hole is defined in the reference layer and under the test point. The signal layer, the insulation layer, and the reference layer are configured in a cascading order. Wherein an arrangement of the signal layer in relation to the reference layer comprising the hole reduces a capacitance effect caused by the test point. A method of manufacturing the printed circuit board is provided.

Abstract: A method and related circuitry for driving output signals of a chip is disclosed. The method includes driving output signals with an even number of inverter driving circuits, and keeping an equivalent load of each inverter of the driving circuits substantially identical by keeping impedances of each driving circuit substantially identical.

Abstract: An output circuit for outputting data with reduced simultaneous switching output skew includes N counts of output buffers and a comparator. The N counts of output buffers receive N counts of bit signals, respectively. At least one of the output buffers includes a delay unit for processing one of the bit signals into a delayed bit signal with an adjustable delay period in response to a delay signal, a pull-up unit electrically connected to the delay unit and a source voltage, and selectively enabled to output the delayed bit signal as a high level, and a pull-down unit electrically connected to the delay unit and a ground voltage, and selectively enabled to output the delayed bit signal as a low level. The comparator is electrically connected to the N counts of output buffers, compares the N counts of bit signals sampled at a first time spot and a second time spot, and generates the delay signal according to the comparing result.

Abstract: An output circuit for outputting data with reduced simultaneous switching output skew includes N counts of output buffers and a comparator. The N counts of output buffers receive N counts of bit signals, respectively. At least one of the output buffers includes a delay unit for processing one of the bit signals into a delayed bit signal with an adjustable delay period in response to a delay signal, a pull-up unit electrically connected to the delay unit and a source voltage, and selectively enabled to output the delayed bit signal as a high level, and a pull-down unit electrically connected to the delay unit and a ground voltage, and selectively enabled to output the delayed bit signal as a low level. The comparator is electrically connected to the N counts of output buffers, compares the N counts of bit signals sampled at a first time spot and a second time spot, and generates the delay signal according to the comparing result.

Abstract: A method and related circuitry for driving output signals of a chip is disclosed. The method includes driving output signals with an even number of inverter driving circuits, and keeping an equivalent load of each inverter of the driving circuits substantially identical by keeping impedances of each driving circuit substantially identical.

Abstract: A signal transmission device which transmits n-bit parallel digital signals through an I/O driver to minimize simultaneous switching noise in an integrated circuit chip is proposed. The signal transmission device includes an encoder coupled to the I/O driver which receives the n-bit parallel digital signals and performs an encoding operation to the n-bit parallel digital signals to provide encoded m-bit parallel digital signals for the I/O driver, where m>n and the encoding operation is performed by a rule that the number of logic-1 bits of the encoded m-bit parallel digital signals is maintained at p and the number of logic-0 bits of the encoded m-bit parallel digital signals is maintained at (m−p), where Cpm>2n and m>p>0, and a decoder coupled to the I/O driver which receives the encoded m-bit parallel digital signals and performs a decoding operation to the encoded m-bit parallel digital signals to restore the n-bit parallel digital signals.

Abstract: A signal transmission device which transmits n-bit parallel digital signals through an I/O driver to minimize simultaneous switching noise in an integrated circuit chip is proposed. The signal transmission device includes an encoder coupled to the I/O driver which receives the n-bit parallel digital signals and performs an encoding operation to the n-bit parallel digital signals to provide encoded m-bit parallel digital signals for the I/O driver, where m>n and the encoding operation is performed by a rule that the number of logic-1 bits of the encoded m-bit parallel digital signals is maintained at p and the number of logic-0 bits of the encoded m-bit parallel digital signals is maintained at (m−p), where Cpm>2n and m>p>0, and a decoder coupled to the I/O driver which receives the encoded m-bit parallel digital signals and performs a decoding operation to the encoded m-bit parallel digital signals to restore the n-bit parallel digital signals.