Abstract: A method for processing data read/write includes receiving a data read/write request. The data read/write request includes a command type, data, an address, a resource identifier, and a priority level. If the read/write request is the read request, determining whether the read request meets a first placement rule, the first rule being that the address of the read request is different from any and all write request addresses in the write command queue. If the first placement rule is not satisfied, the data stored in the conflicting (i.e., duplicated) address of the write request in the write command queue is acquired as the read data. A data read/write processing apparatus and a computer readable medium related to the data read/write processing method are also disclosed.

Abstract: A method for processing data read/write includes receiving a data read/write request. The data read/write request includes a command type, data, an address, a resource identifier, and a priority level. If the read/write request is the read request, determining whether the read request meets a first placement rule, the first rule being that the address of the read request is different from any and all write request addresses in the write command queue. If the first placement rule is not satisfied, the data stored in the conflicting (i.e., duplicated) address of the write request in the write command queue is acquired as the read data. A data read/write processing apparatus and a computer readable medium related to the data read/write processing method are also disclosed.

Abstract: A signal transmitting circuit providing compatibility and stability in signal transmissions across domains with different clock frequencies includes an edge detection circuit, a flip circuit, a synchronization circuit, and an edge extraction circuit. The edge detection circuit detects an edge of an initial interrupt signal and generates an event trigger signal in a faster clock domain. The flip circuit converts the event trigger signal into an edge signal. The synchronization circuit synchronizes the edge signal under a slower clock domain and generates a synchronization signal. The edge extraction circuit generates a trigger signal based on the synchronization signal in the slower clock domain to a target circuit in the slower clock domain. A method and an electronic apparatus related to the signal transmitting circuit are also disclosed.