Abstract: A semiconductor structure includes a first dielectric layer, a first metallic feature over the first dielectric layer, an air gap over the first dielectric layer and adjacent to the first metallic feature, a second dielectric layer disposed above the air gap and on a sidewall of the first metallic feature, and a third dielectric layer disposed above the air gap and on a sidewall of the second dielectric layer. A lower portion of the first metallic feature is exposed in the air gap. The third and the second dielectric layers are substantially co-planar.

Abstract: A method of controlling phase shift pulse width modulation of a power converter, the method includes a step of obtaining sampling signals of an output voltage and current of the power converter. Then, a digital signal processor is used to calculate an output power of the power converter. Next, a comparator is used to compare the output power of the power converter with a reference power. When the output power is less than the reference power, the modulation control of the switch of the power converter enters into hard-switching mode, and when the output power is greater than the reference power, the modulation control of the switch of the power converter enters into soft-switching mode.

Abstract: A semiconductor device includes source and drain regions, a channel region between the source and drain regions, and a gate structure over the channel region. The gate structure includes a gate dielectric over the channel region, a work function metal layer over the gate dielectric and comprising iodine, and a fill metal over the work function metal layer.

Abstract: A flyback power converter includes a power transformer, a first lossless voltage conversion circuit, a first low-dropout linear regulator and a secondary side power supply circuit. The first low-dropout linear regulator (LDO) generates a first operation voltage as power supply for being supplied to a sub-operation circuit. The secondary side power supply circuit includes a second lossless voltage conversion circuit and a second LDO. The second LDO generates a second operation voltage. The first operation voltage and the second operation voltage are shunted to a common node. When a first lossless conversion voltage is greater than a first threshold voltage, the second LDO is enabled to generate the second operation voltage to replace the first operation voltage as power supply supplied to the sub-operation circuit; wherein the second lossless conversion voltage is lower than the first lossless switching voltage.

Abstract: A projection device includes a casing, a projection lens, a light valve module, a light source module, a first heat dissipation module, a second heat dissipation module, a fan, and a guiding member. The first heat dissipation module is disposed corresponding to a first air inlet of a first side cover and connected to the light valve module, and the second heat dissipation module is disposed corresponding to a second air inlet of a second side cover and connected to the light source module. An airflow in an accommodating space of the casing is guided to the guiding member by the fan, and is transferred from the guiding member to an air outlet to flow out of the casing. A direction of an image beam of the projection lens is different from an airflow direction flowing out from the air outlet of a third side cover.

Abstract: A hot spot defect detecting method and a hot spot defect detecting system are provided. In the method, hot spots are extracted from a design of a semiconductor product to define a hot spot map comprising hot spot groups, wherein local patterns in a same context of the design yielding a same image content are defined as a same hot spot group. During runtime, defect images obtained by an inspection tool performing hot scans on a wafer manufactured with the design are acquired and the hot spot map is aligned to each defect image to locate the hot spot groups. The hot spot defects in each defect image are detected by dynamically mapping the hot spot groups located in each defect image to a plurality of threshold regions and respectively performing automatic thresholding on pixel values of the hot spots of each hot spot group in the corresponding threshold region.

Abstract: In some embodiments, the present disclosure relates an integrated chip including a substrate. A conductive interconnect feature is arranged over the substrate. The conductive interconnect feature has a base feature portion with a base feature width and an upper feature portion with an upper feature width. The upper feature width is narrower than the base feature width such that the conductive interconnect feature has tapered outer feature sidewalls. An interconnect via is arranged over the conductive interconnect feature. The interconnect via has a base via portion with a base via width and an upper via portion with an upper via width. The upper via width is wider than the base via width such that the interconnect via has tapered outer via sidewalls.

Abstract: Embodiments of the present disclosure generally relate to a substrate support having a surface coating which reduces defect formation and back side metal contamination during substrate processing. A support body includes a body having an outer surface and a surface coating formed from a non-metal or a reduced-metal material disposed over at least a top surface of the outer surface of the body. In an embodiment, the surface coating includes a two-part coating having an optional first coating layer formed over an entire outer surface of the support body.

Abstract: A textile fabric includes a textile fabric layer, a transparent film layer provided on the textile fabric layer, and a surface layer disposed on the transparent film layer. The transparent film layer has a two-layer structure including a first film layer having a first polyetherester-based copolymer and a second film layer having a second polyetherester-based copolymer disposed on the first film layer. The second film layer is provided on the textile fabric layer. A method of manufacturing the fabric includes preparing the textile fabric layer, forming the transparent film layer on the fabric layer, and laminating the textile fabric and transparent film layers through heat treatment.

Abstract: A projection device includes a casing, a light source module, a light valve module, a projection lens, a heat dissipation module, and a fan disposed in the casing. The casing has at least one air inlet, a first air outlet, and a second air outlet. The heat dissipation module is coupled to the light source module and the light valve module and configured to cool the light source module and the light valve module. The fan has a first air exhaust and a second air exhaust. The first air exhaust and the second air exhaust are respectively disposed at positions adjacent to the first air outlet and the second air outlet of the casing.

Abstract: A radio frequency receiving circuit includes a first amplification circuit, an oscillation circuit, a frequency mixing and amplification circuit and a dividing circuit. The first amplification circuit is configured to amplify an input signal so as to generate an amplified input signal. The oscillation circuit is configured to provide a local oscillation signal. The frequency mixing and amplification circuit is configured to mix and amplify the amplified input signal according to the local oscillation signal. The dividing circuit is configured to form a dividing loop at a preset frequency for the amplified input signal according to the local oscillation signal when the dividing circuit is driven. A chip including the radio frequency receiving circuit and a main circuit is also provided. The main circuit is configured to drive the dividing circuit when the second input signal is determined to include a signal of the preset frequency.

Abstract: Different isolation liners for different type FinFETs and associated isolation feature fabrication are disclosed herein. An exemplary method includes performing a fin etching process on a substrate to form first trenches defining first fins in a first region and second trenches defining second fins in a second region. An oxide liner is formed over the first fins in the first region and the second fins in the second region. A nitride liner is formed over the oxide liner in the first region and the second region. After removing the nitride liner from the first region, an isolation material is formed over the oxide liner and the nitride liner to fill the first trenches and the second trenches. The isolation material, the oxide liner, and the nitride liner are recessed to form first isolation features (isolation material and oxide liner) and second isolation features (isolation material, nitride liner, and oxide liner).

Abstract: An image sensor chip with depth information is provided. The image sensor chip includes an SPAD array, a time-to-digital converter module, a storage circuit, and a data processing circuit. The SPAD array includes a plurality of image sensor units, and each of the image sensor units includes a plurality of SPAD units and a decision circuit, wherein each of the SPAD units outputs a photon detection result within a scan period, and the decision circuit generates an image-sensing signal based on the photon detection results. The time-to-digital converter module generates a plurality of first time data in response to the image-sensing signals. The storage circuit stores the first time data temporarily. The data processing unit reads the first time data from the storage circuit and generates a plurality of second time data in response to the first time data.

Abstract: A touchpad module includes a base plate, a touch member and at least one pressure sensing module. The touch member is located over the base plate. The touch member includes a touch plate and a touch sensitive circuit board. The pressure sensing module is arranged between the base plate and the touch member. The pressure sensing module includes a pressure sensor and a miniature supporting plate. The pressure sensor is installed on the miniature supporting plate. The pressure sensor is electrically connected with the touch sensitive circuit board through the miniature supporting plate. While the touch member is pressed in response to an external pressing force, the pressing force exerted on the touch member is sensed by the at least one pressure sensing module, and the pressure sensing module generates a pressure sensing signal.

Abstract: A method includes removing a first dummy gate structure to form a recess around a first nanostructure and a second nanostructure; depositing a sacrificial layer in the recess with a flowable chemical vapor deposition (CVD); and patterning the sacrificial layer to leave a portion of the sacrificial layer between the first nanostructure and the second nanostructure. The method further include depositing a first work function metal in first recess; removing the first work function metal and the portion of the sacrificial layer from the recess; depositing a second work function metal in the recess, wherein the second work function metal is of an opposite type than the first work function metal; and depositing a fill metal over the second work function metal in the recess.

Abstract: Disclosed are an electrolyte membrane of a membrane-electrode assembly including an electronic insulation layer, which greatly improves the durability of the electrolyte membrane, and a method of preparing the same. The electrolyte membrane includes an ion exchange layer and an electronic insulation layer provided on the ion exchange layer, and the electronic insulation layer includes one or more catalyst complexes, and a second ionomer Particularly, each of the one or more catalyst complex includes a catalyst particle and a first ionomer coated on the entirety or a portion of the surface of the catalyst particle, and the one or more catalyst complexes are dispersed the second ionomer.

Abstract: Microelectromechanical devices and methods of manufacture are presented. Embodiments include bonding a mask substrate to a first microelectromechanical system (MEMS) device. After the bonding has been performed, the mask substrate is patterned. A first conductive pillar is formed within the mask substrate, and a second conductive pillar is formed within the mask substrate, the second conductive pillar having a different height from the first conductive pillar. The mask substrate is then removed.

Abstract: A display panel including a circuit board, a plurality of bonding pads, a plurality of light emitting devices, and a plurality of solder patterns is provided. The bonding pads are disposed on the circuit board, and each includes a first metal layer and a second metal layer. The second metal layer is located between the first metal layer and the circuit board. The first metal layer includes an opening overlapping the second metal layer. A material of the first metal layer is different from a material of the second metal layer. The light emitting devices are electrically bonded to the bonding pads. Each of the solder patterns electrically connects one of the light emitting devices and one of the bonding pads. The solder patterns each contact the second metal layer through the opening of the first metal layer of one of the bonding pads to form a eutectic bonding.

Abstract: Some embodiments include a reticle which includes first pattern features and second pattern features. A first optimal dose of actinic radiation is associated with the first pattern features and a second optimal dose of the actinic radiation is associated with the second pattern features. The second pattern features are larger than the first pattern features. Each of the second pattern features has a configuration which includes a central region laterally surrounded by an outer region, with the central region being of different opacity than the outer region. The configurations of the second pattern features balance the second optimal dose of the actinic radiation to be within about 5% of the first optimal dose of the actinic radiation. Some embodiments include photo-processing methods.

Abstract: A light-emitting device is provided. The light-emitting device includes a light-emitting unit and a light-conversion structure disposed on the light-emitting unit, wherein the light-conversion structure includes a quantum dot layer and an etching blocking layer disposed on one of the surfaces of the quantum dot layer.