Patents by Inventor Yi-Li Lin

Yi-Li Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240145398
    Abstract: A carrier structure is provided, in which at least one positioning area is defined on a chip-placement area of a package substrate, and at least one alignment portion is disposed on the positioning area. Therefore, the precision of manufacturing the alignment portion is improved by disposing the positioning area on the chip-placement area, such that the carrier structure can provide a better alignment mechanism for the chip placement operation.
    Type: Application
    Filed: December 8, 2022
    Publication date: May 2, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Cheng-Liang HSU, Wan-Rou CHEN, Hsin-Yin CHANG, Tsung-Li LIN, Hsiu-Jung LI, Chiu-Lien LI, Fu-Quan XU, Yi-Wen LIU, Chih-Chieh SUN
  • Publication number: 20240132887
    Abstract: Disclosed herein are, inter alia, inhibitors of protein arginine methyltransferase 9 and pharmaceutical compositions thereof, and methods comprising the use of protein arginine methyltransferase 9 inhibitors for the treatment of a protein arginine methyltransferase 9-modulated disease or disorder, such as a hematological cancer.
    Type: Application
    Filed: October 6, 2023
    Publication date: April 25, 2024
    Applicants: City of Hope, Western University of Health Sciences
    Inventors: Ling Li, Haojie Dong, Lei Zhang, Xin He, Yun Lyna Luo, Yi-Chun Lin
  • Publication number: 20240113188
    Abstract: An integrated circuit (IC) structure includes a semiconductor substrate, a first gate line, a second gate line, and a first auxiliary gate portion. The semiconductor substrate comprises a semiconductor fin. The semiconductor fin extends substantially along a first direction. The first gate line and the second gate line extend substantially along a second direction different form the first direction from a top view. The first auxiliary gate portion connects the first gate line to the second gate line from the top view.
    Type: Application
    Filed: March 27, 2023
    Publication date: April 4, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wen-Li CHIU, Yi-Juei LEE, Yu-Jie YE, Chi-Hsin CHANG, Chun-Jun LIN
  • Patent number: 11938678
    Abstract: Disclosed herein are an adhesion blocking element, a three-dimensional printing device and a three-dimensional printing method. The adhesion blocking element comprises: one light-transmittable main body comprising a first surface and a second surface which are disposed opposite to each other, and side faces connecting the first surface and the second surface; and a plurality of microstructures arranged on the main body, wherein each microstructure has one cavity formed in the main body and one first open face which is arranged on the first surface of the main body and communicated to the cavity. The present invention decreases the adhesion between the adhesion blocking element and the cured layer by improving the structure of the adhesion blocking element itself, and eliminates the negative pressure adsorption between the cured layer and the adhesion blocking element, so that it is easier to peel the adhesion blocking element off from the cured layer.
    Type: Grant
    Filed: May 5, 2019
    Date of Patent: March 26, 2024
    Assignee: LUXCREO (BEIJING) INC.
    Inventors: Guang Zhu, Zhifeng Yao, Fang Li, Yi-Ho Lin, Yanhui Guo, Hu Wang
  • Publication number: 20240067740
    Abstract: The present disclosure provides antibodies and antibody fragments thereof that bind to human TNFR2. The disclosed antibodies, inhibit the TNF-TNFR2 signaling axis and enhance cytokine secretion in T effector cells and are therefore useful for the treatment of cancer, either alone or in combination with other agents.
    Type: Application
    Filed: December 30, 2021
    Publication date: February 29, 2024
    Inventors: Yi PEI, Haichun HUANG, Ming LEI, Han LI, Chi Shing SUM, Alla PRITSKER, Bor-Ruei LIN, Fangqiang TANG
  • Publication number: 20220379269
    Abstract: The invention discloses a forward osmosis (FO) membrane containing silica nanoparticles having high permeate water flux and its manufacturing method. The FO membrane containing a plurality of silica nanoparticles comprises a substrate layer made of polysulfone and a polyamide layer disposed on the substrate layer. In the course of manufacturing the polyamide layer on the substrate layer by interfacial polymerization, the plurality of silica nanoparticles with different properties is added into the polyamide layer to obtain the FO membrane containing silica nanoparticles having high permeability and solute selectivity.
    Type: Application
    Filed: November 3, 2021
    Publication date: December 1, 2022
    Inventors: YI-LI LIN, TRUC-QUYNH NGUYEN, KUO-LUN TUNG, CHENG-DI DONG, CHIU-WEN CHEN, CHUNG-HSIN WU
  • Patent number: 9167528
    Abstract: A power saving method for a mobile device in a wireless communication system is disclosed. The power saving method comprises detecting a screen status of the mobile device and switching to different connection states according to the screen status of the mobile device when the mobile device has no data transmission and reception.
    Type: Grant
    Filed: March 22, 2013
    Date of Patent: October 20, 2015
    Assignee: HTC Corporation
    Inventors: Wen-Jui Hsieh, Ching-Hao Lee, Yi-Li Lin, Chang-Hsin Su
  • Publication number: 20130252674
    Abstract: A power saving method for a mobile device in a wireless communication system is disclosed. The power saving method comprises detecting a screen status of the mobile device and switching to different connection states according to the screen status of the mobile device when the mobile device has no data transmission and reception.
    Type: Application
    Filed: March 22, 2013
    Publication date: September 26, 2013
    Applicant: HTC CORPORATION
    Inventors: Wen-Jui Hsieh, Ching-Hao Lee, Yi-Li Lin, Chang-Hsin Su
  • Patent number: 8130006
    Abstract: An electronic element testing apparatus for use with a number of probes. Each probe has a lower pole and an upper pole. The apparatus includes: a first plate having a first side and a second side, the first side having an array of lower pole regions disposed thereabout, each lower pole region configured to receive a lower pole of a probe; and a plurality of signal conductor regions disposed proximate the array of lower pole regions, each signal conductor region arranged to provide a non-cable electrical path between a lower pole region and a switching circuit. The switching circuits are operable to sequentially connect each electronic element to a testing circuit via the upper and lower poles.
    Type: Grant
    Filed: January 12, 2010
    Date of Patent: March 6, 2012
    Assignee: Vishay General Semiconductor, inc.
    Inventors: Kuang-Jung Li, Chin-Chen Hsu, Yi-Li Lin, Shyan-I Wu
  • Publication number: 20100109692
    Abstract: An electronic element testing apparatus for use with a number of probes. Each probe has a lower pole and an upper pole. The apparatus includes: a first plate having a first side and a second side, the first side having an array of lower pole regions disposed thereabout, each lower pole region configured to receive a lower pole of a probe; and a plurality of signal conductor regions disposed proximate the array of lower pole regions, each signal conductor region arranged to provide a non-cable electrical path between a lower pole region and a switching circuit. The switching circuits are operable to sequentially connect each electronic element to a testing circuit via the upper and lower poles.
    Type: Application
    Filed: January 12, 2010
    Publication date: May 6, 2010
    Applicant: VISHAY GENERAL SEMICONDUCTOR, INC.
    Inventors: Kuang-Jung LI, Chin-Chen HSU, Yi-Li Lin, Shyan-I Wu
  • Patent number: 7671611
    Abstract: An electronic element testing apparatus for use with a number of probes. Each probe has a lower pole and an upper pole. The apparatus includes: a first plate having a first side and a second side, the first side having an array of lower pole regions disposed thereabout, each lower pole region configured to receive a lower pole of a probe; and a plurality of signal conductor regions disposed proximate the array of lower pole regions, each signal conductor region arranged to provide a non-cable electrical path between a lower pole region and a switching circuit. The switching circuits are operable to sequentially connect each electronic element to a testing circuit via the upper and lower poles.
    Type: Grant
    Filed: February 13, 2008
    Date of Patent: March 2, 2010
    Assignee: Vishay General Semiconductor LLC
    Inventors: Kuang-Jung Li, Chin-Chen Hsu, Yi-Li Lin, Shyan-I Wu
  • Publication number: 20080136431
    Abstract: An electronic element testing apparatus for use with a number of probes. Each probe has a lower pole and an upper pole. The apparatus includes: a first plate having a first side and a second side, the first side having an array of lower pole regions disposed thereabout, each lower pole region configured to receive a lower pole of a probe; and a plurality of signal conductor regions disposed proximate the array of lower pole regions, each signal conductor region arranged to provide a non-cable electrical path between a lower pole region and a switching circuit. The switching circuits are operable to sequentially connect each electronic element to a testing circuit via the upper and lower poles.
    Type: Application
    Filed: February 13, 2008
    Publication date: June 12, 2008
    Applicant: Vishay General Semiconductor, Inc.
    Inventors: Kuang-Jung Li, Chin-Chen Hsu, Yi-Li Lin, Shyan-l Wu
  • Patent number: 7374293
    Abstract: An electronic element testing apparatus for use with a number of probes. Each probe has a lower pole and an upper pole. The apparatus includes: a first plate having a first side and a second side, the first side having an array of lower pole regions disposed thereabout, each lower pole region configured to receive a lower pole of a probe; and a plurality of signal conductor regions disposed proximate the array of lower pole regions, each signal conductor region arranged to provide a non-cable electrical path between a lower pole region and a switching circuit. The switching circuits are operable to sequentially connect each electronic element to a testing circuit via the upper and lower poles.
    Type: Grant
    Filed: March 25, 2005
    Date of Patent: May 20, 2008
    Assignee: Vishay General Semiconductor Inc.
    Inventors: Kuang-Jung Li, Chin-Chen Hsu, Yi-Li Lin, Shyan-I Wu