Patents by Inventor Yi-Li Lin
Yi-Li Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145398Abstract: A carrier structure is provided, in which at least one positioning area is defined on a chip-placement area of a package substrate, and at least one alignment portion is disposed on the positioning area. Therefore, the precision of manufacturing the alignment portion is improved by disposing the positioning area on the chip-placement area, such that the carrier structure can provide a better alignment mechanism for the chip placement operation.Type: ApplicationFiled: December 8, 2022Publication date: May 2, 2024Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Cheng-Liang HSU, Wan-Rou CHEN, Hsin-Yin CHANG, Tsung-Li LIN, Hsiu-Jung LI, Chiu-Lien LI, Fu-Quan XU, Yi-Wen LIU, Chih-Chieh SUN
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Publication number: 20240132887Abstract: Disclosed herein are, inter alia, inhibitors of protein arginine methyltransferase 9 and pharmaceutical compositions thereof, and methods comprising the use of protein arginine methyltransferase 9 inhibitors for the treatment of a protein arginine methyltransferase 9-modulated disease or disorder, such as a hematological cancer.Type: ApplicationFiled: October 6, 2023Publication date: April 25, 2024Applicants: City of Hope, Western University of Health SciencesInventors: Ling Li, Haojie Dong, Lei Zhang, Xin He, Yun Lyna Luo, Yi-Chun Lin
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Publication number: 20240113188Abstract: An integrated circuit (IC) structure includes a semiconductor substrate, a first gate line, a second gate line, and a first auxiliary gate portion. The semiconductor substrate comprises a semiconductor fin. The semiconductor fin extends substantially along a first direction. The first gate line and the second gate line extend substantially along a second direction different form the first direction from a top view. The first auxiliary gate portion connects the first gate line to the second gate line from the top view.Type: ApplicationFiled: March 27, 2023Publication date: April 4, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wen-Li CHIU, Yi-Juei LEE, Yu-Jie YE, Chi-Hsin CHANG, Chun-Jun LIN
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Patent number: 11938678Abstract: Disclosed herein are an adhesion blocking element, a three-dimensional printing device and a three-dimensional printing method. The adhesion blocking element comprises: one light-transmittable main body comprising a first surface and a second surface which are disposed opposite to each other, and side faces connecting the first surface and the second surface; and a plurality of microstructures arranged on the main body, wherein each microstructure has one cavity formed in the main body and one first open face which is arranged on the first surface of the main body and communicated to the cavity. The present invention decreases the adhesion between the adhesion blocking element and the cured layer by improving the structure of the adhesion blocking element itself, and eliminates the negative pressure adsorption between the cured layer and the adhesion blocking element, so that it is easier to peel the adhesion blocking element off from the cured layer.Type: GrantFiled: May 5, 2019Date of Patent: March 26, 2024Assignee: LUXCREO (BEIJING) INC.Inventors: Guang Zhu, Zhifeng Yao, Fang Li, Yi-Ho Lin, Yanhui Guo, Hu Wang
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Publication number: 20240067740Abstract: The present disclosure provides antibodies and antibody fragments thereof that bind to human TNFR2. The disclosed antibodies, inhibit the TNF-TNFR2 signaling axis and enhance cytokine secretion in T effector cells and are therefore useful for the treatment of cancer, either alone or in combination with other agents.Type: ApplicationFiled: December 30, 2021Publication date: February 29, 2024Inventors: Yi PEI, Haichun HUANG, Ming LEI, Han LI, Chi Shing SUM, Alla PRITSKER, Bor-Ruei LIN, Fangqiang TANG
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Publication number: 20220379269Abstract: The invention discloses a forward osmosis (FO) membrane containing silica nanoparticles having high permeate water flux and its manufacturing method. The FO membrane containing a plurality of silica nanoparticles comprises a substrate layer made of polysulfone and a polyamide layer disposed on the substrate layer. In the course of manufacturing the polyamide layer on the substrate layer by interfacial polymerization, the plurality of silica nanoparticles with different properties is added into the polyamide layer to obtain the FO membrane containing silica nanoparticles having high permeability and solute selectivity.Type: ApplicationFiled: November 3, 2021Publication date: December 1, 2022Inventors: YI-LI LIN, TRUC-QUYNH NGUYEN, KUO-LUN TUNG, CHENG-DI DONG, CHIU-WEN CHEN, CHUNG-HSIN WU
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Patent number: 9167528Abstract: A power saving method for a mobile device in a wireless communication system is disclosed. The power saving method comprises detecting a screen status of the mobile device and switching to different connection states according to the screen status of the mobile device when the mobile device has no data transmission and reception.Type: GrantFiled: March 22, 2013Date of Patent: October 20, 2015Assignee: HTC CorporationInventors: Wen-Jui Hsieh, Ching-Hao Lee, Yi-Li Lin, Chang-Hsin Su
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Publication number: 20130252674Abstract: A power saving method for a mobile device in a wireless communication system is disclosed. The power saving method comprises detecting a screen status of the mobile device and switching to different connection states according to the screen status of the mobile device when the mobile device has no data transmission and reception.Type: ApplicationFiled: March 22, 2013Publication date: September 26, 2013Applicant: HTC CORPORATIONInventors: Wen-Jui Hsieh, Ching-Hao Lee, Yi-Li Lin, Chang-Hsin Su
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Patent number: 8130006Abstract: An electronic element testing apparatus for use with a number of probes. Each probe has a lower pole and an upper pole. The apparatus includes: a first plate having a first side and a second side, the first side having an array of lower pole regions disposed thereabout, each lower pole region configured to receive a lower pole of a probe; and a plurality of signal conductor regions disposed proximate the array of lower pole regions, each signal conductor region arranged to provide a non-cable electrical path between a lower pole region and a switching circuit. The switching circuits are operable to sequentially connect each electronic element to a testing circuit via the upper and lower poles.Type: GrantFiled: January 12, 2010Date of Patent: March 6, 2012Assignee: Vishay General Semiconductor, inc.Inventors: Kuang-Jung Li, Chin-Chen Hsu, Yi-Li Lin, Shyan-I Wu
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Publication number: 20100109692Abstract: An electronic element testing apparatus for use with a number of probes. Each probe has a lower pole and an upper pole. The apparatus includes: a first plate having a first side and a second side, the first side having an array of lower pole regions disposed thereabout, each lower pole region configured to receive a lower pole of a probe; and a plurality of signal conductor regions disposed proximate the array of lower pole regions, each signal conductor region arranged to provide a non-cable electrical path between a lower pole region and a switching circuit. The switching circuits are operable to sequentially connect each electronic element to a testing circuit via the upper and lower poles.Type: ApplicationFiled: January 12, 2010Publication date: May 6, 2010Applicant: VISHAY GENERAL SEMICONDUCTOR, INC.Inventors: Kuang-Jung LI, Chin-Chen HSU, Yi-Li Lin, Shyan-I Wu
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Patent number: 7671611Abstract: An electronic element testing apparatus for use with a number of probes. Each probe has a lower pole and an upper pole. The apparatus includes: a first plate having a first side and a second side, the first side having an array of lower pole regions disposed thereabout, each lower pole region configured to receive a lower pole of a probe; and a plurality of signal conductor regions disposed proximate the array of lower pole regions, each signal conductor region arranged to provide a non-cable electrical path between a lower pole region and a switching circuit. The switching circuits are operable to sequentially connect each electronic element to a testing circuit via the upper and lower poles.Type: GrantFiled: February 13, 2008Date of Patent: March 2, 2010Assignee: Vishay General Semiconductor LLCInventors: Kuang-Jung Li, Chin-Chen Hsu, Yi-Li Lin, Shyan-I Wu
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Publication number: 20080136431Abstract: An electronic element testing apparatus for use with a number of probes. Each probe has a lower pole and an upper pole. The apparatus includes: a first plate having a first side and a second side, the first side having an array of lower pole regions disposed thereabout, each lower pole region configured to receive a lower pole of a probe; and a plurality of signal conductor regions disposed proximate the array of lower pole regions, each signal conductor region arranged to provide a non-cable electrical path between a lower pole region and a switching circuit. The switching circuits are operable to sequentially connect each electronic element to a testing circuit via the upper and lower poles.Type: ApplicationFiled: February 13, 2008Publication date: June 12, 2008Applicant: Vishay General Semiconductor, Inc.Inventors: Kuang-Jung Li, Chin-Chen Hsu, Yi-Li Lin, Shyan-l Wu
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Patent number: 7374293Abstract: An electronic element testing apparatus for use with a number of probes. Each probe has a lower pole and an upper pole. The apparatus includes: a first plate having a first side and a second side, the first side having an array of lower pole regions disposed thereabout, each lower pole region configured to receive a lower pole of a probe; and a plurality of signal conductor regions disposed proximate the array of lower pole regions, each signal conductor region arranged to provide a non-cable electrical path between a lower pole region and a switching circuit. The switching circuits are operable to sequentially connect each electronic element to a testing circuit via the upper and lower poles.Type: GrantFiled: March 25, 2005Date of Patent: May 20, 2008Assignee: Vishay General Semiconductor Inc.Inventors: Kuang-Jung Li, Chin-Chen Hsu, Yi-Li Lin, Shyan-I Wu