Abstract: The present invention discloses a fabrication method of substrate on chip CA BGA package, wherein a chip is installed on a first surface of each substrate unit of a substrate with the front face of the chip attached with the first surface. The area of the substrate units arranged in a matrix array is smaller than that of the chip. Next, a plurality of leads are used to connect the front faces of the chips with second surfaces of the substrate units by wire bonding. Finally, several solder bumps are formed on the second surfaces of the substrate units between the leads. After the dicing step, the obtained package structure conforms to the requirement of real chip scale package. The present invention can also enhance the throughput, achieve better reliability, and lower the cost.

Abstract: The present invention provides a stacked chip scale package structure, wherein a lower chip and an upper chip are stacked on a substrate. Two rows of bonding pads are disposed on each of the upper and lower chips. The bonding pads on the upper and lower chips are parallel arranged. At least a dummy die is disposed below the suspended portion of the upper chip and at the side of the lower chip as a support during wire bonding. A gap is reserved between the dummy die and the lower chip. The present invention utilizes the design of dummy die to resolve the problem of die crack caused by wire bonding of suspended chip. Therefore, the present invention can flexibly adjust the size and installation direction of the upper chip to meet the requirement of substrate layout, and can also shorten the trace length on the substrate to enhance the electric performance thereof.

Abstract: The present invention provides a design structure of an plated wire of a fiducial mark for a die-dicing package. In the present structure, a cutting line is positioned between each two adjacent ball grid array (BGA) chips. There is configured a solder mask opening at the edge connecting region of the cutting lines. A fiducial mark is positioned in the opening of each BGA chip, wherein the fiducial mark is close to the cutting line and positioned a plated wire therein to pull from the fiducial mark to out the opening and to connect to the plated wire of the cutting line. So as all the plated wires utilizing the coverage of the solder mask can be entirely cut without the pulling problem from the cutter. The present invention provides a new design structure of the plated wire to overcome the burr effect of prior die dicing so as to enhance the product efficiency and decrease the manufacturing cost.

Abstract: A dual-sided heat dissipating structure for BGA package includes a step-shaped first heat dissipating member adhering to an active side of the chip and a dish-shaped perforated second heat dissipating member adhering to a non-active side of the chip so that heat generated in the chip may be dissipated more effectively. The step surface first heat dissipating member may also serve as a press mold to enable bonding of inner leads of the substrate to the bonding pads of the chip be done along with adhering of the first heat dissipating member to the chip at same process in the mean time without additional process or equipment. The perforated second heat dissipating member enables moisture escaping from the package to avoid pop corn effect resulting from IR Reflow test. The package may be made at a thin thickness and low cost.

Abstract: An enhanced heat dissipating Chip Scale Package (CSP) method and devices include preparing a heat dissipating base with a recess surrounded by a guarding wall. A chip with an integrated circuit (IC) layout is adhered the heat dissipating base in the recess. A substrate with a metallic circuit layer that is smaller size than the chip is then adhered to the chip. Then coupling the metallic circuit layer with the IC layout. A non-conductive resin is then filled in the recess within the guarding wall and covers the coupling portion. The resulting package device produced by means of BGA package process is small size and has enhanced heat dissipating property. The Package size/chip size ratio may be lower than 1.2 to meet the CSP requirements.

Abstract: A thin enhanced TAB BGA package includes an IC chip, a substrate having a center opening and one side laid with a metallic circuitry which has a plurality of inner leads extending to the center opening, a plurality of metallic solder balls attached to the substrate at one side and coupling with the metallic circuitry, and a heat dissipating member adhering partly to the a side of the chip and partly to the substrate for heat dissipating, positioning and supporting the IC chip and the substrate. The IC chip has a another side exposed to ambience to add heat dissipating effect. The heat dissipating member has about same thickness as the substrate. Hence the ball grid array package may be made of a small size and thin thickness. The adhering of heat dissipating member to the chip and substrate may be done at the same process of bonding the inner leads to the IC chip. Thus the thin enhanced TAB BGA package of this invention may be produced at low cost without additional equipment or process.