Patents by Inventor YI-LIANG YE
YI-LIANG YE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10892348Abstract: A method of rounding fin-shaped structures includes the following steps. A substrate including fin-shaped structures, and pad oxide caps and pad nitride caps covering the fin-shaped structures from bottom to top are provided. An isolation structure fills between the fin-shaped structures. A removing process is performed to remove a top part of the isolation structure and expose top parts of the fin-shaped structures. An oxidation process is performed to oxidize sidewalls of the top parts of the fin-shaped structures, thereby forming oxidized parts covering sidewalls of the top parts of the fin-shaped structures. The pad nitride caps are removed. The pad oxide caps and the oxidized parts are removed at the same time, thereby forming rounding fin-shaped structures.Type: GrantFiled: April 29, 2019Date of Patent: January 12, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hao-Hsuan Chang, Bin-Siang Tsai, Ting-An Chien, Yi-Liang Ye
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Publication number: 20200343371Abstract: A method of rounding fin-shaped structures includes the following steps. A substrate including fin-shaped structures, and pad oxide caps and pad nitride caps covering the fin-shaped structures from bottom to top are provided. An isolation structure fills between the fin-shaped structures. A removing process is performed to remove a top part of the isolation structure and expose top parts of the fin-shaped structures. An oxidation process is performed to oxidize sidewalls of the top parts of the fin-shaped structures, thereby forming oxidized parts covering sidewalls of the top parts of the fin-shaped structures. The pad nitride caps are removed. The pad oxide caps and the oxidized parts are removed at the same time, thereby forming rounding fin-shaped structures.Type: ApplicationFiled: April 29, 2019Publication date: October 29, 2020Inventors: Hao-Hsuan Chang, Bin-Siang Tsai, Ting-An Chien, Yi-Liang Ye
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Patent number: 10796943Abstract: A manufacturing method of a semiconductor structure includes the following steps. A patterned mask layer is formed on a semiconductor substrate. An isolation trench is formed in the semiconductor substrate by removing a part of the semiconductor substrate. A liner layer is conformally formed on an inner sidewall of the isolation trench. An implantation process is performed to the liner layer. The implantation process includes a noble gas implantation process. An isolation structure is at least partially formed in the isolation trench after the implantation process. An etching process is performed to remove the patterned mask layer after forming the isolation structure and expose a top surface of the semiconductor substrate. A part of the liner layer formed on the inner sidewall of the isolation trench is removed by the etching process. The implantation process is configured to modify the etch rate of the liner layer in the etching process.Type: GrantFiled: November 6, 2018Date of Patent: October 6, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yi-Liang Ye, Chun-Wei Yu, Yu-Ren Wang, Shi-You Liu, Shao-Hua Hsu
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Patent number: 10651174Abstract: A method of forming a gate structure on a fin structure includes the steps of providing a fin structure covered by a first silicon oxide layer, a silicon nitride layer, a gate material and a cap material in sequence, wherein the silicon nitride layer contacts the first silicon oxide layer. Later, the cap material is patterned to form a first cap layer and the gate material is patterned to form a first gate electrode by taking the silicon nitride layer as an etching stop layer. Then, the silicon nitride layer not covered by the first gate electrode is removed to expose part of the first silicon oxide layer. Finally, a first dielectric layer is formed to conformally cover the first silicon oxide layer, the first gate electrode and the first cap layer.Type: GrantFiled: May 14, 2019Date of Patent: May 12, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yi-Liang Ye, Kuang-Hsiu Chen, Chun-Wei Yu, Chueh-Yang Liu, Yu-Ren Wang
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Publication number: 20200144102Abstract: A manufacturing method of a semiconductor structure includes the following steps. A patterned mask layer is formed on a semiconductor substrate. An isolation trench is formed in the semiconductor substrate by removing a part of the semiconductor substrate. A liner layer is conformally formed on an inner sidewall of the isolation trench. An implantation process is performed to the liner layer. The implantation process includes a noble gas implantation process. An isolation structure is at least partially formed in the isolation trench after the implantation process. An etching process is performed to remove the patterned mask layer after forming the isolation structure and expose a top surface of the semiconductor substrate. A part of the liner layer formed on the inner sidewall of the isolation trench is removed by the etching process. The implantation process is configured to modify the etch rate of the liner layer in the etching process.Type: ApplicationFiled: November 6, 2018Publication date: May 7, 2020Inventors: Yi-Liang Ye, Chun-Wei Yu, Yu-Ren Wang, Shi-You Liu, Shao-Hua Hsu
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Patent number: 10622481Abstract: A method of rounding corners of a fin includes providing a substrate with a fin protruding from the substrate, wherein a pad oxide and a pad nitride entirely cover a top surface of the fin. Later, part of the pad oxide is removed laterally to expose part of the top surface of the fin. A silicon oxide layer is formed to contact two sidewalls of the fin and the exposed top surface, wherein two sidewalls and the top surface define two corners of the fin. After forming the silicon oxide layer, an annealing process is performed to round two corners of the fin. Finally, after the annealing process, an STI filling material is formed to cover the pad nitride, the pad oxide and the fin.Type: GrantFiled: August 7, 2018Date of Patent: April 14, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yi-Liang Ye, Chun-Wei Yu, Yu-Ren Wang, Hao-Hsuan Chang, Chia-Wei Hsu
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Publication number: 20200052123Abstract: A method of rounding corners of a fin includes providing a substrate with a fin protruding from the substrate, wherein a pad oxide and a pad nitride entirely cover a top surface of the fin. Later, part of the pad oxide is removed laterally to expose part of the top surface of the fin. A silicon oxide layer is formed to contact two sidewalls of the fin and the exposed top surface, wherein two sidewalls and the top surface define two corners of the fin. After forming the silicon oxide layer, an annealing process is performed to round two corners of the fin. Finally, after the annealing process, an STI filling material is formed to cover the pad nitride, the pad oxide and the fin.Type: ApplicationFiled: August 7, 2018Publication date: February 13, 2020Inventors: Yi-Liang Ye, Chun-Wei Yu, Yu-Ren Wang, Hao-Hsuan Chang, Chia-Wei Hsu
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Patent number: 10446667Abstract: A method for fabricating semiconductor device includes the steps of: forming a first gate structure on a substrate; performing a first etching process to form a recess adjacent to the first gate structure; performing an ion implantation process to form an amorphous layer directly under the recess; performing a second etching process to remove the amorphous layer; and forming an epitaxial layer in the recess.Type: GrantFiled: May 7, 2019Date of Patent: October 15, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yu-Ying Lin, Yi-Liang Ye, Sung-Yuan Tsai, Chun-Wei Yu, Yu-Ren Wang, Zhen Wu, Tai-Yen Lin
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Publication number: 20190279979Abstract: A method of forming a gate structure on a fin structure includes the steps of providing a fin structure covered by a first silicon oxide layer, a silicon nitride layer, a gate material and a cap material in sequence, wherein the silicon nitride layer contacts the first silicon oxide layer. Later, the cap material is patterned to form a first cap layer and the gate material is patterned to form a first gate electrode by taking the silicon nitride layer as an etching stop layer. Then, the silicon nitride layer not covered by the first gate electrode is removed to expose part of the first silicon oxide layer. Finally, a first dielectric layer is formed to conformally cover the first silicon oxide layer, the first gate electrode and the first cap layer.Type: ApplicationFiled: May 14, 2019Publication date: September 12, 2019Inventors: Yi-Liang Ye, Kuang-Hsiu Chen, Chun-Wei Yu, Chueh-Yang Liu, Yu-Ren Wang
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Publication number: 20190280106Abstract: A method for fabricating semiconductor device includes the steps of: forming a first gate structure on a substrate; performing a first etching process to form a recess adjacent to the first gate structure; performing an ion implantation process to form an amorphous layer directly under the recess; performing a second etching process to remove the amorphous layer; and forming an epitaxial layer in the recess.Type: ApplicationFiled: May 7, 2019Publication date: September 12, 2019Inventors: Yu-Ying Lin, Yi-Liang Ye, Sung-Yuan Tsai, Chun-Wei Yu, Yu-Ren Wang, Zhen Wu, Tai-Yen Lin
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Patent number: 10340268Abstract: A method of forming a gate structure on a fin structure includes the steps of providing a fin structure covered by a first silicon oxide layer, a silicon nitride layer, a gate material and a cap material in sequence, wherein the silicon nitride layer contacts the first silicon oxide layer. Later, the cap material is patterned to form a first cap layer and the gate material is patterned to form a first gate electrode by taking the silicon nitride layer as an etching stop layer. Then, the silicon nitride layer not covered by the first gate electrode is removed to expose part of the first silicon oxide layer. Finally, a first dielectric layer is formed to conformally cover the first silicon oxide layer, the first gate electrode and the first cap layer.Type: GrantFiled: October 4, 2016Date of Patent: July 2, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yi-Liang Ye, Kuang-Hsiu Chen, Chun-Wei Yu, Chueh-Yang Liu, Yu-Ren Wang
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Patent number: 10332981Abstract: A method for fabricating semiconductor device includes the steps of: forming a first gate structure on a substrate; performing a first etching process to form a recess adjacent to the first gate structure; performing an ion implantation process to form an amorphous layer directly under the recess; performing a second etching process to remove the amorphous layer; and forming an epitaxial layer in the recess.Type: GrantFiled: April 2, 2018Date of Patent: June 25, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yu-Ying Lin, Yi-Liang Ye, Sung-Yuan Tsai, Chun-Wei Yu, Yu-Ren Wang, Zhen Wu, Tai-Yen Lin
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Patent number: 10332741Abstract: A method for post chemical mechanical polishing clean is provided in the present invention, which include the steps of providing a substrate, performing a chemical mechanical polishing process, and performing a plurality of cleaning processes sequentially substrate using solutions of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2) with different ratios and at different temperatures.Type: GrantFiled: May 8, 2017Date of Patent: June 25, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yi-Liang Ye, Kuang-Hsiu Chen, Chun-Wei Yu, Yu-Ren Wang
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Patent number: 10312084Abstract: A method for fabricating the semiconductor device is disclosed. A semiconductor substrate having a main surface is provided. A gate is formed on the main surface of the semiconductor substrate. An offset liner is formed on the sidewall of the gate. An ion implantation process is performed to form lightly doped drain (LDD) region in the semiconductor substrate. A spacer is formed on a sidewall of the gate. A cavity is recessed into the main surface of the semiconductor substrate. The cavity is adjacent to the spacer. An epitaxial layer is grown in the cavity. The spacer is then subjected to a surface treatment to form a dense oxide film on the spacer. A mask layer is deposited on the dense oxide film. The dense oxide film has a thickness that is smaller or equal to 12 angstroms.Type: GrantFiled: February 22, 2017Date of Patent: June 4, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kuang-Hsiu Chen, Yi-Liang Ye, Chueh-Yang Liu, Yu-Ren Wang
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Publication number: 20180323058Abstract: A method for post chemical mechanical polishing clean is provided in the present invention, which include the steps of providing a substrate, performing a chemical mechanical polishing process, and performing a plurality of cleaning processes sequentially substrate using solutions of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2) with different ratios and at different temperatures.Type: ApplicationFiled: May 8, 2017Publication date: November 8, 2018Inventors: Yi-Liang Ye, Kuang-Hsiu Chen, Chun-Wei Yu, Yu-Ren Wang
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Patent number: 9966266Abstract: An apparatus for semiconductor wafer treatment includes a wafer holding unit configured to receive a single wafer, at least a solution supply unit configured to apply a solution onto the wafer and an irradiation unit configured to emit irradiation to the wafer. The irradiation unit further includes at least a plurality of first light sources configured to emit irradiation in FIR range and a plurality of second light sources configured to emit irradiation in UV range.Type: GrantFiled: April 25, 2016Date of Patent: May 8, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yu-Ying Lin, Chueh-Yang Liu, Yu-Ren Wang, Chun-Wei Yu, Kuang-Hsiu Chen, Yi-Liang Ye, Hsu Ting, Neng-Hui Yang
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Publication number: 20180122707Abstract: The present invention provides a method for forming a semiconductor device, comprising the following steps: firstly, a substrate is provided, having a NMOS region and a PMOS region defined thereon, next, a gate structure is formed on the substrate within the NMOS region, and a disposal spacer is formed on two sides of the gate structure, afterwards, a mask layer is formed on the PMOS region to expose the NMOS region, next, a recess is formed on two sides of the gate structure spaced from the gate structure by the disposal spacer within the NMOS region, the disposal spacer is then removed after the recess is formed, and an epitaxial layer is formed into the recess.Type: ApplicationFiled: November 1, 2016Publication date: May 3, 2018Inventors: Yi-Liang Ye, Kuang-Hsiu Chen, Chun-Wei Yu, Chueh-Yang Liu, Wen-Jiun Shen, Yu-Ren Wang
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Patent number: 9960084Abstract: The present invention provides a method for forming a semiconductor device, comprising the following steps: firstly, a substrate is provided, having a NMOS region and a PMOS region defined thereon, next, a gate structure is formed on the substrate within the NMOS region, and a disposal spacer is formed on two sides of the gate structure, afterwards, a mask layer is formed on the PMOS region to expose the NMOS region, next, a recess is formed on two sides of the gate structure spaced from the gate structure by the disposal spacer within the NMOS region, the disposal spacer is then removed after the recess is formed, and an epitaxial layer is formed into the recess.Type: GrantFiled: November 1, 2016Date of Patent: May 1, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yi-Liang Ye, Kuang-Hsiu Chen, Chun-Wei Yu, Chueh-Yang Liu, Wen-Jiun Shen, Yu-Ren Wang
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Publication number: 20180096995Abstract: A method of forming a gate structure on a fin structure includes the steps of providing a fin structure covered by a first silicon oxide layer, a silicon nitride layer, a gate material and a cap material in sequence, wherein the silicon nitride layer contacts the first silicon oxide layer. Later, the cap material is patterned to form a first cap layer and the gate material is patterned to form a first gate electrode by taking the silicon nitride layer as an etching stop layer. Then, the silicon nitride layer not covered by the first gate electrode is removed to expose part of the first silicon oxide layer. Finally, a first dielectric layer is formed to conformally cover the first silicon oxide layer, the first gate electrode and the first cap layer.Type: ApplicationFiled: October 4, 2016Publication date: April 5, 2018Inventors: Yi-Liang Ye, Kuang-Hsiu Chen, Chun-Wei Yu, Chueh-Yang Liu, Yu-Ren Wang
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Patent number: 9899520Abstract: A method for forming a semiconductor device includes steps as follows: Firstly, a semiconductor substrate having a circuit element with at least one spacer formed thereon is provided. Next, an acid treatment is performed on a surface of the spacer. A disposable layer is then formed on the circuit element and the spacer. Thereafter, an etching process is performed to form at least one recess in the semiconductor substrate adjacent to the circuit element. Subsequently, a selective epitaxial growth (SEG) process is performed to form an epitaxial layer in the recess.Type: GrantFiled: December 22, 2015Date of Patent: February 20, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yi-Liang Ye, Kuang-Hsiu Chen, Chueh-Yang Liu, Yu-Ren Wang