Abstract: A semiconductor device comprises a first gate electrode on a substrate, a first conductive contact on the first gate electrode, an etch stop layer (ESL) on the first conductive contact, and a second conductive contact extending through the ESL. The first conductive contact has a first width. The second conductive contact has a second width, the second width being smaller than the first width. The ESL overhangs a portion of the second conductive contact. A convex bottom surface of the second conductive contact physically contacts a concave top surface of the first conductive contact.

Abstract: A semiconductor device comprises a first gate electrode on a substrate, a first conductive contact on the first gate electrode, an etch stop layer (ESL) on the first conductive contact, and a second conductive contact extending through the ESL. The first conductive contact has a first width. The second conductive contact has a second width, the second width being smaller than the first width. The ESL overhangs a portion of the second conductive contact. A convex bottom surface of the second conductive contact physically contacts a concave top surface of the first conductive contact.

Abstract: A semiconductor device includes a first dielectric layer, a cobalt-containing conductive feature, a non-cobalt conductive feature, a second dielectric layer, a first tungsten contact feature, a second tungsten contact feature, and a tungsten barrier layer. The cobalt-containing conductive feature is disposed in the first dielectric layer. The non-cobalt conductive feature is disposed in the first dielectric layer, and is spaced apart from the cobalt-containing conductive feature. The second dielectric layer is disposed over the first dielectric layer. The first tungsten contact feature is disposed in the second dielectric layer, and is electrically connected to the cobalt-containing conductive feature. The second tungsten contact feature is disposed in the second dielectric layer, and is electrically connected to the non-cobalt conductive feature.

Abstract: The present disclosure describes semiconductor devices and methods for forming the same. A method for forming a semiconductor device includes forming a source/drain structure and forming a gate structure. The method also includes performing a cleaning process on the source/drain structure and the gate structure. The method also includes disposing a portion of a byproduct of the cleaning process on a top surface of the gate structure and etching the portion of the byproduct so a remaining portion of the byproduct is formed on the top surface of the gate structure. The method further includes forming a gate contact structure, including depositing a metal material on the remaining portion of the byproduct to form a compound containing the metal material and the remaining portion of the byproduct. The method also includes forming a barrier layer between the compound and the top surface of the gate structure.

Abstract: A semiconductor device comprises a first gate electrode on a substrate, a first conductive contact on the first gate electrode, an etch stop layer (ESL) on the first conductive contact, and a second conductive contact extending through the ESL. The first conductive contact has a first width. The second conductive contact has a second width, the second width being smaller than the first width. The ESL overhangs a portion of the second conductive contact. A convex bottom surface of the second conductive contact physically contacts a concave top surface of the first conductive contact.

Abstract: A semiconductor device includes a first dielectric layer, a cobalt-containing conductive feature, a non-cobalt conductive feature, a second dielectric layer, a first tungsten contact feature, a second tungsten contact feature, and a tungsten barrier layer. The cobalt-containing conductive feature is disposed in the first dielectric layer. The non-cobalt conductive feature is disposed in the first dielectric layer, and is spaced apart from the cobalt-containing conductive feature. The second dielectric layer is disposed over the first dielectric layer. The first tungsten contact feature is disposed in the second dielectric layer, and is electrically connected to the cobalt-containing conductive feature. The second tungsten contact feature is disposed in the second dielectric layer, and is electrically connected to the non-cobalt conductive feature.

Abstract: A method of forming a semiconductor structure includes; (i) forming an isolation structure in a semiconductor substrate, the isolation structure electrically isolating device regions of the semiconductor substrate; (ii) forming a gate structure extending from one of the device regions to the isolation structure; (iii) forming a resist protective oxide layer overlaying the gate structure and the isolation structure; and (iv) patterning the resist protective oxide layer to form a patterned resist protective oxide that covers at least a portion of the isolation structure and a portion of the gate structure on the isolation structure.

Abstract: A method of forming a semiconductor structure includes; (i) forming an isolation structure in a semiconductor substrate, the isolation structure electrically isolating device regions of the semiconductor substrate; (ii) forming a gate structure extending from one of the device regions to the isolation structure; (iii) forming a resist protective oxide layer overlaying the gate structure and the isolation structure; and (iv) patterning the resist protective oxide layer to form a patterned resist protective oxide that covers at least a portion of the isolation structure and a portion of the gate structure on the isolation structure.

Abstract: The semiconductor device structures and methods for forming the same are provided. The semiconductor device structure includes a metal gate over a substrate. A first spacer is formed over sidewalls of the metal gate and having a first height. A second spacer is formed over the sidewalls of the metal gate and having a second height. The first height is higher than the second height. The first spacer is farther from the sidewalls of the metal gate than the second spacer. In addition, the semiconductor device structure includes a dielectric layer formed over the substrate to surround the first spacer and the metal gate.

Abstract: A semiconductor structure includes an isolation structure, a gate stack, a spacer and a patterned resist protective oxide. The isolation structure is formed in a semiconductor substrate, and electrically isolates device regions of the semiconductor substrate. The gate stack is located on the isolation structure. The spacer is formed along a sidewall of the gate stack on the isolation structure. The patterned resist protective oxide is located on the isolation structure and covers a sidewall of the spacer such that the spacer is interposed between the patterned resist protective oxide and the gate stack.

Abstract: A semiconductor structure includes an isolation structure, a gate stack, a spacer and a patterned resist protective oxide. The isolation structure is formed in a semiconductor substrate, and electrically isolates device regions of the semiconductor substrate. The gate stack is located on the isolation structure. The spacer is formed along a sidewall of the gate stack on the isolation structure. The patterned resist protective oxide is located on the isolation structure and covers a sidewall of the spacer such that the spacer is interposed between the patterned resist protective oxide and the gate stack.

Abstract: The integrated circuit (IC) device includes a substrate, an isolation feature, a first gate structure, a second gate structure, a first contact feature and a first supplementary active region. The isolation feature is disposed in the substrate, and the isolation feature defines a boundary between a first active region and a second active region of the substrate. The first gate structure is disposed over the first active region. The second gate structure is disposed over the second active region. The first contact feature is disposed over the first active region, in which a portion of the first active region is disposed between the first gate structure and the isolation feature. The first supplementary active region is disposed adjacent to the portion of the first active region, in which a thickness of the first supplementary active region is substantially in a range from 5 nm to 10 nm.

Abstract: The semiconductor device structures and methods for forming the same are provided. The semiconductor device structure includes a metal gate over a substrate. A first spacer is formed over sidewalls of the metal gate and having a first height. A second spacer is formed over the sidewalls of the metal gate and having a second height. The first height is higher than the second height. The first spacer is farther from the sidewalls of the metal gate than the second spacer. In addition, the semiconductor device structure includes a dielectric layer formed over the substrate to surround the first spacer and the metal gate.

Abstract: The semiconductor device structures and methods for forming the same are provided. The semiconductor device structure includes a metal gate over a substrate. A first spacer is formed over sidewalls of the metal gate and having a first height. A second spacer is formed over the sidewalls of the metal gate and having a second height. The first height is higher than the second height. The first spacer is farther from the sidewalls of the metal gate than the second spacer. In addition, the semiconductor device structure includes a dielectric layer formed over the substrate to surround the first spacer and the metal gate.

Abstract: The semiconductor device structures and methods for forming the same are provided. The semiconductor device structure includes a metal gate over a substrate. A first spacer is formed over sidewalls of the metal gate and having a first height. A second spacer is formed over the sidewalls of the metal gate and having a second height. The first height is higher than the second height. The first spacer is farther from the sidewalls of the metal gate than the second spacer. In addition, the semiconductor device structure includes a dielectric layer formed over the substrate to surround the first spacer and the metal gate.

Abstract: Embodiments of the disclosure provide semiconductor device structures and methods of forming the same. The semiconductor device structure includes a metal gate over a substrate. A first spacer is formed over sidewalls of the metal gate and having a first height. A second spacer is formed over the sidewalls of the metal gate and having a second height. The first height is higher than the second height. The first spacer is farther from the sidewalls of the metal gate than the second spacer. In addition, the semiconductor device structure includes a dielectric layer formed over the substrate to surround the first spacer and the metal gate.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes an isolation structure positioned in the semiconductor substrate and adjacent to a first active region of the semiconductor substrate. The semiconductor device structure includes a gate stack disposed over the first active region. The semiconductor device structure includes a first contact structure disposed over the first active region and positioned between the isolation structure and the gate stack. The semiconductor device structure includes a dummy gate stack disposed over the isolation structure and adjacent to the gate stack. The dummy gate stack is not positioned over a portion of the isolation structure next to the first contact structure.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes an isolation structure positioned in the semiconductor substrate and adjacent to a first active region of the semiconductor substrate. The semiconductor device structure includes a gate stack disposed over the first active region. The semiconductor device structure includes a first contact structure disposed over the first active region and positioned between the isolation structure and the gate stack. The semiconductor device structure includes a dummy gate stack disposed over the isolation structure and adjacent to the gate stack. The dummy gate stack is not positioned over a portion of the isolation structure next to the first contact structure.

Abstract: The integrated circuit (IC) device includes a substrate, an isolation feature, a first gate structure, a second gate structure, a first contact feature and a first supplementary active region. The isolation feature is disposed in the substrate, and the isolation feature defines a boundary between a first active region and a second active region of the substrate. The first gate structure is disposed over the first active region. The second gate structure is disposed over the second active region. The first contact feature is disposed over the first active region, in which a portion of the first active region is disposed between the first gate structure and the isolation feature. The first supplementary active region is disposed adjacent to the portion of the first active region, in which a thickness of the first supplementary active region is substantially in a range from 5 nm to 10 nm.

Abstract: A method includes forming a photodiode in a substrate and forming source and drain regions in the substrate. A first rapid thermal anneal (RTA) process is performed to anneal the source and drain regions in the substrate. After forming the source and drain regions, a thermal oxide layer is grown over the photodiode by performing a second RTA process. A thickness of the thermal oxide layer is limited to a thickness required to enclose a damaged portion of a surface of the photodiode.