Abstract: A window structure is provided, comprising a frame, a solar energy board, a plate and a heat isolation film. The solar energy board is disposed in the frame. The plate is disposed in the frame corresponding to the solar energy board, wherein an isolation chamber is formed between the plate and the solar energy board. The heat isolation film is disposed between the solar energy board and the plate, and divides the isolation chamber.

Abstract: A fan includes an impeller, a motor, a plurality of first engaging members and a plurality of second engaging members. The impeller includes a hub and a plurality of blades disposed around the hub. The motor includes a rotor housing coupled with the hub, and the motor is for driving the impeller to rotate. The first engaging members are disposed on an inner side of the top surface of the hub, and the second engaging members are disposed on the top surface of the housing. When the impeller and the rotor housing are assembled, the second engaging members are disposed corresponding to the first engaging members, so that parts of the first engaging members are engaged into and assembled with the second engaging members.

Abstract: A voltage stabilizing circuit for chips and the method thereof are disclosed. The circuit and the method thereof are applied to chips with at least one non-wire bonded I/O circuit. The driver circuit of the I/O circuit includes a plurality of transistors. The method of voltage stabilizing involves causing at least one of these transistors to start conducting in order to generate a stabilizing capacitor. Therefore, chip damages caused by voltage or current fluctuations can be avoided, simultaneously reducing the cost and the amount of chip surface area being consumed.

Abstract: The present invention relates to a metal-oxide-semiconductor field-effect transistor (MOSFET) with electrostatic-discharge (ESD) protection and a voltage-stabilizing capacitor, and a method for manufacturing the same and is applied to a chip, including a P-type substrate, a conductor layer, a first N-type doping region, a second N-type doping region, and an N-type well. The conductor layer is coupled to the ground; the first N-type doping region is coupled to the power supply; the second N-type doping region is coupled to a VDD pad (power-supply pad). Thereby, when the chip is not installed or not operating, the MOSFET can be used for ESD protection. When the chip is operating, the conductor layer, the first N-type doping region, the second N-type doing region, and the N-type well form a gate capacitor as a voltage-stabilizing capacitor between the power supply and the ground. Hence, the objective of fully utilization is achieved. In addition, the chip size is saved and thus the cost thereof is reduced.

Abstract: A digital circuit system includes: a register, for receiving and registering digital data; an operation unit, for operating and generating resulting data according to the digital data registered in the first registering unit; a second register, for receiving and registering the resulting data; a multi-phase clock signal generating unit, for generating a plurality of reference clock signals having different phases with each other; a first selector, for selecting one of the reference clock signals to output a first clock signal to the first registering unit; and a second selector, for selecting another of the reference clock signals to output a second clock signal to the second registering unit.

Abstract: The present invention provides an output signal driving circuit, which includes: a comparator coupled to a reference voltage for comparing the reference voltage and a voltage level of an output terminal to output a comparison signal; a first switch having a terminal coupled to a first supply voltage and having another terminal coupled to an output terminal, wherein the conductivity of the first switch depends on a first input signal and the comparison signal, for selectively conducting the second supply voltage to the output terminal; wherein the first supply voltage is not less than the reference voltage.

Abstract: An output signal driving circuit is provided. The output signal driving circuit includes a first switch, a second switch, a third switch, and a fourth switch. The first switch is for selectively conducting a first supply voltage with a first terminal according to a first control signal. The second switch is for selectively conducting a second supply voltage with a second terminal according to a second control signal. The third switch is for selectively conducting the first terminal with an output terminal of the output signal driving circuit according to a third reference voltage. The fourth switch is for selectively conducting the second terminal with the output terminal according to a fourth reference voltage. The voltage level of both the third and the fourth reference voltages are between voltage levels of the first and the second supply voltages.

Abstract: A sampling circuit includes a sampling unit, a first delay chain, an inverter, and a second delay chain. The sampling unit detects edge triggers of a first delayed signal and a second delayed signal for sampling input data to generate output data signal; the first delay chain is coupled to the sampling unit for delaying a sampling clock signal to output the first delayed signal; the inverter inverts the sampling clock signal to generate an inverted sampling clock signal; and the second delay chain is coupled to the inverter and the sampling unit for delaying the inverted sampling clock signal to output the second delayed signal.

Abstract: A memory controller includes an output buffer for receiving a clock signal and outputting the clock signal to an external memory; and a replica buffer for receiving the clock signal and outputting the clock signal to a counting circuit; wherein the replica buffer and the output buffer have the same delay time such that the clock signal received by the counting circuit can be synchronized with that received by the external memory, and therefore the counting circuit can accurately count to a predetermined time according to the clock signal and output an enabling signal to enable a data control signal. The present invention further provides a signal synchronizing method for the memory controller.

Abstract: A circuit for calibrating a data control signal comprises a time-delay compensation circuit and a voltage-control delay circuit. The time-delay compensation circuit receives two complementary signals and a direct current voltage which has two voltage cross points with the two complementary signals respectively, and outputs a control voltage according to a time difference between the two voltage cross points. The voltage-control delay circuit delays a data control signal for a predetermined time according to the control voltage, thereby eliminating signal skew between the data control signal and a data signal.

Abstract: A memory controller for controlling a memory, where the memory controller includes: a pad, coupled to the memory, for generating an output signal to the memory according to a signal value of the memory controller; a voltage pull-up device, coupled to the pad, comprising a first N type transistor and for pulling up a voltage level on the pad according to the signal value; and a voltage pull-down device, coupled to the pad, comprising a second N type transistor and for pulling down the voltage level on the pad according to the signal value.

Abstract: Disclosed is an output driver, which comprises: a resistance element with resistance, coupled to an output terminal; a current mode driving circuit, coupled to the resistance element, for providing a first current to the output terminal, wherein at least one of the amount of the first current and the resistance of the resistance element is adjusted according to a control signal; and a control circuit for generating the control signal according to a mode signal, wherein the mode signal corresponds to at least two technology standards.

Abstract: The present invention provides a device for ESD protection and voltage stabilizing in order to let chip space be put in better utilization. During different conditions (i.e. ESD current occurrences and normal operation), identical elements of the device are used both for ESD protection and for voltage stabilization. The chip size and manufacturing costs necessary for the additional voltage stabilizing capacitors are thereby saved.

Abstract: The present invention relates to a signal transferring system. The signal transferring system includes a first and second layout paths, and a first and second circuits. Lengths of the first and second layout paths are different. The first and second circuits are used for transmitting and receiving at least two signals respectively. In addition, one of the first circuit and the second circuit includes a compensation circuit for adjusting transmission time of one of the at least two transferred signals or adjusting reception time of one of the at least two transferred signals such that the at least two transferred signals reach a second circuit through the first and the second layout paths at substantially the same time.

Abstract: A signal sampling apparatus for a DRAM memory comprises a phase delay circuit adapted for receiving a data signal and delaying the data signal by a predetermined time to generate a delay signal; and a sampling circuit for sampling the data signal according to the delay signal.

Abstract: A real-time calibrating circuit comprises a first comparator, a second comparator, a phase detector, at least one control circuit, and at least one output driving circuit for driving a data control signal or a data signal, wherein the first and the second comparators compare the voltage values of two complementary signals and a direct-current voltage and respectively output a first comparison signal and a second comparison signal according to the results of comparing the voltage values; the phase detector outputs a phase difference signal according to the phase difference of the first and second comparison signals; the control circuit adjusts the output driving circuit according to the phase difference signal, whereby calibrating the data control signal or the data signal. The present invention also provides a real-time calibrating method for a data control signal and a data signal.

Abstract: A new method is provided for the creation of an alignment mark. V-groove etching is applied whereby this anisotropic etch stops at the (1,1,1) crystal direction of the silicon of the substrate. The invention applies a wet etchant to the surface of monocrystalline silicon of the silicon substrate by using a solution containing a mixture of potassium hydroxide (KOH) or N2H4 or tetramethyl ammonium hydroxide (TMAH). This solution anisotropically etches the silicon substrate, forming grooves in the substrate having sidewalls that are sloped at an angle of about 54 degrees with the horizontal. The slope of the sidewalls is a function of the different etch rates of monocrystalline silicon along the different crystalline orientations. The surface of the substrate represents <100> planes of the silicon, which etches faster than the sloped sidewalls that represent the <111> plane. The KOH/N2H4/TMAH etch stops on the <111> plane of the silicon substrate.

Abstract: A new method is provided for the creation of a dummy pattern. A typical wafer exposure mask contains a Clear Out Window (CLWD) pattern, this CLWD pattern is of no value during the process of shielding the area on the surface of the wafer where the alignment mark must be placed. This CLWD can therefore be used to create a dummy overlay pattern, resulting in a reduction in the wafer scaling error that typically occurs as a result of metal deposition. For the same reasons, a dummy overlay pattern can also be created in the scribe lines of the wafer surface.

Abstract: An electrostatic discharge protection circuit coupled between an I/O pad and an internal circuit of an IC. The electrostatic discharge protection circuit includes a first diode having a positive end coupled to the I/O pad, and a negative end coupled to a first supply voltage; a second diode having a positive end coupled to a second supply voltage, and a negative end coupled to the I/O pad; and a third diode having a positive end coupled to the second supply voltage, and a negative end coupled to the first-supply voltage. The breakdown voltage of the third diode is substantially smaller than the breakdown voltage of the first diode or the breakdown voltage of the second diode.