Patents by Inventor Yi-Lin Hsu

Yi-Lin Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160225882
    Abstract: A method of manufacturing an isolation structure suitable for a non-volatile memory is provided. A substrate is provided. A dielectric layer, a conductive layer, and a hard mask layer are sequentially formed on the substrate. The hard mask layer and the conductive layer are patterned to form a first trench which exposes the dielectric layer. A first liner is formed on the substrate. The first liner and the dielectric layer that are exposed by the first trench are removed to expose the substrate. A spacer is formed on sidewalls of the conductive layer and the hard mask layer. The substrate is partly removed to form a second trench with use of the conductive layer and the hard mask layer with the spacer as a mask. An isolation layer is formed in the second trench. The distance between the conductive layers is greater than the width of the second trench.
    Type: Application
    Filed: April 21, 2015
    Publication date: August 4, 2016
    Inventors: Chun-Yu Chuang, Yi-Lin Hsu, Liang-Chuan Lai
  • Patent number: 9406784
    Abstract: A method of manufacturing an isolation structure suitable for a non-volatile memory is provided. A substrate is provided. A dielectric layer, a conductive layer, and a hard mask layer are sequentially formed on the substrate. The hard mask layer and the conductive layer are patterned to form a first trench which exposes the dielectric layer. A first liner is formed on the substrate. The first liner and the dielectric layer that are exposed by the first trench are removed to expose the substrate. A spacer is formed on sidewalls of the conductive layer and the hard mask layer. The substrate is partly removed to form in a second trench with use of the conductive layer and the hard mask layer with the spacer as a mask. An isolation layer is formed in the second trench. The distance between the conductive layers is greater than the width of the second trench.
    Type: Grant
    Filed: April 21, 2015
    Date of Patent: August 2, 2016
    Assignee: Powerchip Technology Corporation
    Inventors: Chun-Yu Chuang, Yi-Lin Hsu, Liang-Chuan Lai